User manual

ATHENA CPU User Manual V1.40 Page 38
10.2 Data Acquisition Circuit Register Map
WRITE (Blank bits are unused and have no effect)
Address 7 6 5 4 3 2 1 0
0 STRTAD RSTBRD RSTDA RSTFIFO CLRDMA CLRT CLRD CLRA
1
2 H3 H2 H1 H0 L3 L2 L1 L0
3 SCANEN G1 G0
4 CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DINTE AINTE
5 FT5 FT4 FT3 FT2 FT1 FT0
6 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
7 DACH1 DACH0 DA11 DA10 DA9 DA8
8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
9 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
10 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
11 DIOCTR DIRA DIRCH DIRB DIRCL
12 CTRD7 CTRD6 CTRD5 CTRD4 CTRD3 CTRD2 CTRD1 CTRD0
13 CTRD15 CTRD14 CTRD13 CTRD12 CTRD11 CTRD10 CTRD9 CTRD8
14 CTRD23 CTRD22 CTRD21 CTRD20 CTRD19 CTRD18 CTRD17 CTRD16
15 CTRNO LATCH GTDIS GTEN CTDIS CTEN LOAD CLR
READ (Blank bits are unused and read back as 0)
Address 7 6 5 4 3 2 1 0
0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
2 H3 H2 H1 H0 L3 L2 L1 L0
3 STS SD WAIT DACBSY OVF SCANEN G1 G0
4 CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DINTE AINTE
5 FT5 FT4 FT3 FT2 FT1 FT0
6 FD5 FD4 FD3 FD2 FD1 FD0
7 DMAINT TINT DINT AINT ADCH3 ADCH2 ADCH1 ADCH0
8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
9 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
10 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
11 DIOCTR DIRA DIRCH DIRB DIRCL
12 CTRD7 CTRD6 CTRD5 CTRD4 CTRD3 CTRD2 CTRD1 CTRD0
13 CTRD15 CTRD14 CTRD13 CTRD12 CTRD11 CTRD10 CTRD9 CTRD8
14 CTRD23 CTRD22 CTRD21 CTRD20 CTRD19 CTRD18 CTRD17 CTRD16
15 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0