User manual

ATHENA CPU User Manual V1.40 Page 37
10.1 Base Address
The data acquisition circuitry on Athena occupies a block of 16 bytes in I/O memory space. The
default address range for this block is 280h – 28Fh (base address 280).
The data acquisition FPGA can be enabled/disabled in the BIOS under the Advanced menu.
Scroll down to the “FPGA Mode:” option and select “Enabled” or “Disabled” accordingly. If the
FPGA is disabled you will not be able to interact with the data acquisition circuit.
The FPGA can be enabled or disabled programmatically through the CPLD. More information is
on page 26.
A functional list of registers is provided below, and detailed bit definitions are provided on the next
page and in the following chapter.
Base + Write Function Read Function
0 Command register A/D LSB
1 Not used A/D MSB
2 A/D channel register A/D channel register
3 A/D gain and scan settings A/D gain and status readback
4 Interrupt / DMA / counter control Interrupt / DMA / counter control readback
5 FIFO threshold FIFO threshold readback
6 D/A LSB FIFO current depth
7 D/A MSB + channel no. Interrupt and A/D channel readback
8 Digital I/O port A output Digital I/O port A
9 Digital I/O port B output Digital I/O port B
10 Digital I/O port C output Digital I/O port C
11 Digital I/O direction control Digital I/O direction control readback
12 Counter/timer D7-0 Counter/timer D7-0
13 Counter/timer D15-8 Counter/timer D15-8
14 Counter/timer D23-16 Counter/timer D23-16
15 Counter/timer control register FPGA revision code