User manual

ATHENA CPU User Manual V1.40 Page 36
10. DATA ACQUISITION CIRCUIT – I/O MAP AND REGISTER DESCRIPTIONS
Models ATH400-128 and ATH660-128 contain a data acquisition subsystem consisting of A/D,
D/A, digital I/O, and counter/timer features. This subsystem is equivalent to a complete add-on
data acquisition module.
The A/D section includes a 16-bit A/D converter, 16 input channels, and a 48-sample FIFO. Input
ranges are programmable, and the maximum sampling rate is 100KHz. The D/A section includes
4 12-bit D/A channels. The digital I/O section includes 24 lines with programmable direction. The
counter/timer section includes a 24-bit counter/timer to control A/D sampling rates and a 16-bit
counter/timer for user applications.
High-speed A/D sampling is supported with interrupts and a FIFO. The FIFO is used to store a
user-selected number of samples, and the interrupt occurs when the FIFO reaches this threshold.
Once the interrupt occurs, an interrupt routine runs and reads the data out of the FIFO. In this
way the interrupt rate is reduced by a factor equal to the size of the FIFO threshold, enabling a
faster A/D sampling rate. The circuit can operate at sampling rates of up to 100KHz, with an
interrupt rate of 6.6-10KHz.
The A/D circuit uses the default settings of I/O address range 280h – 28Fh (base address 280)
and IRQ 5. These settings can be changed if needed. The I/O address range is changed in the
BIOS, and the interrupt level is changed with jumper block J10.