User manual

ATHENA CPU User Manual V1.40 Page 26
6.2 COM Port / FPGA / Watchdog Control Registers
A registers located at address 0x25F is used for the purposes of controlling the serial port, FPGA
and watchdog features:
Register Map Bit Assignments
A blank bit in the write registers is unused. A blank bit in the read registers reads back as 0 or 1,
unknown state.
WRITE
Address 7 6 5 4 3 2 1 0
0x25F COM4EN COM3EN FPGAEN WDEN
READ
Address 7 6 5 4 3 2 1 0
0x25F COM4EN COM3EN FPGAEN WDEN
Table 17: I/O COM3/4 Control Register Definition
0x25F Write Chip select enable/disable
Bit No. 7 6 5 4 3 2 1 0
Name
COM4EN COM3EN FPGAEN WDEN
COM4EN COM4 chip select enable. 1 = enable COM4-CS#. 0 = disable COM4-CS#.
COM3EN COM3 chip select enable. 1 = enable COM3-CS#. 0 = disable COM3-CS#.
FPGEN FPGA chip select enable. 1 = enable FPGA-CS#. 0 = disable FPGA-CS#.
WDEN Watchdog enable. 1 = WDT counter enable. 0 = WDT counter disable, WDO
disable, WDI disable, CPURST# disable, EXTSMI# disable.
The CPLD initializes all values to zero on power up. The BIOS then enables each
resource based on BIOS settings.
0x25F Read Chip select enable/disable
Bit No. 7 6 5 4 3 2 1 0
Name
COM4EN COM3EN FPGAEN WDEN
Reads back written values