GF ATHENA™ High Integration CPU with Ethernet and Data Acquisition Model ATH400-128, ATH400-128N, ATH660-128, ATH660-128N User Manual Revision 1.40 Document # 765820 Copyright 2004 Diamond Systems Corporation 8430-D Central Ave. Newark, CA 94560 Tel (510) 456-7800 www.diamondsystems.
ATHENA High-Performance Rugged Embedded CPU with Data Acquisition TABLE OF CONTENTS 1. 2. 3. 4. DESCRIPTION ..................................................................................................................................5 FEATURES .......................................................................................................................................6 ATHENA BOARD DRAWING ......................................................................................................
12.1 Select the input channel ............................................................................................................52 12.2 Select the input range................................................................................................................52 12.3 Wait for analog input circuit to settle .......................................................................................52 12.4 Perform an A/D conversion on the current channel ........................................
TABLES Table 1: J1,J2 – PC/104 Connector Pinouts ....................................................................................9 Table 2: J3 – Main I/O Connector ..................................................................................................10 Table 3: J11 – Input Power Connector Pinout................................................................................12 Table 4: J12 – Output Power Connector Pinout ........................................................................
ATHENA High-Performance Rugged Embedded CPU with Data Acquisition 1. DESCRIPTION Athena is an embedded CPU board in a modified PC/104 form factor that integrates a complete embedded PC, consisting of the following subsystems onto a single compact board: ♦ CPU ♦ Core PC Chipset (including memory controller, PCI interface, and ISA interface) ♦ Video ♦ Sound ♦ Ethernet ♦ Analog I/O A detailed list of features is shown on the next page.
2. FEATURES System Features Processor Section ♦ Via Eden Processor running at 400MHz or 660MHz with integrated math co-processor ♦ Pentium-class platform including SDRAM, IDE controller and USB Core System ♦ 128MB SDRAM system memory (standard) ♦ 100MHz memory bus ♦ 2MB 16-bit wide integrated flash memory for BIOS and user programs ♦ 2D VGA Video graphics engine (VESA-style VGA output with DDC Monitor support) I/O ♦ ♦ 4 RS-232 serial ports, 115.
Data Acquisition Subsystem Analog Input ♦ 16 single-ended / 8 differential inputs, 16-bit resolution ♦ 100KHz maximum aggregate A/D sampling rate ♦ Programmable input ranges/gains with maximum range of ±10V / 0-10V ♦ Both bipolar and unipolar input ranges ♦ 10 ppm/ C drift accuracy ♦ Internal and external A/D triggering ♦ 48-sample FIFO for reliable high-speed sampling and scan operation o Analog Output ♦ 4 analog outputs, 12-bit resolution ♦ ±10V and 0-10V output ranges ♦ ±5V and 0-5V o
3.
4. I/O HEADERS All cables mentioned in this chapter are included in Diamond Systems’ cable kit C-ATH-KIT. These cables are further described in chapter 23. Some cables are also available individually. 4.1 PC/104 Bus Connectors The PC/104 bus is essentially identical to the ISA Bus except for the physical design. It specifies two pin and socket connectors for the bus signals.
4.2 Main I/O Connector – J3 An 80-pin high-density connector is provided for access to the user I/O. The following functions are supported by this connector: ♦ 2 serial ports ♦ PS/2 keyboard ♦ ATX Power switch ♦ Parallel port ♦ PS/2 mouse ♦ Reset switch ♦ Watchdog timer I/O ♦ IrDA port ♦ Power and HDD LEDs The connector mates with Diamond Systems’ cable no. C-PRZ-01, which consists of a dualribbon-cable assembly with industry-standard connectors at the user end.
Notes on J3 Signals COM1 – COM4 The signals on these pins are RS-232 level signals and may be connected directly to RS-232 devices. The pinout of these signals is designed to allow a 9-pin male IDC connector to be crimped onto the corresponding ribbon cable wires to provide the correct pinout for a PC serial port connector (DTE). LPT1 The signals on these pins comprise a standard PC parallel port.
4.3 Input Power – J11 1 2 3 4 5 6 7 8 9 +5V In Ground Ground +12V In Ground +5V In -12V In -5V In ATX Control Table 3: J11 – Input Power Connector Pinout Input power for Athena may be supplied either through J11 from an external supply or directly through the PC/104 bus power pins if a PC/104 power supply is used with the CPU. Athena requires only +5VDC input power to operate. All other required voltages are generated on board with miniature switching regulators.
4.4 Output Power – J12 1 2 3 4 +5V Out Ground Ground +12V Out Table 4: J12 – Output Power Connector Pinout J12 provides switched power for use with external drives. If ATX is enabled, the power is switched on and off with the ATX input switch. If ATX is not enabled, the power is switched on and off in conjunction with the external power. Diamond Systems’ cable no. 698006 mates with J12.
4.7 Watchdog Features – J6 1 2 3 Ground WDI WDO Table 7: J6 – Watchdog Connector Pinout J6 is used for watchdog timer access. The watchdog timer circuit is described on page 66 of this manual. It may be programmed directly, as described in this user manual, or with Diamond Systems’ Universal Driver software. 4.
4.9 Data Acquisition I/O Connector – J14 (Models with Data Acquisition only) Athena includes a 50-pin header labeled J14 for all data acquisition I/O. This header is located on the left side of the board. Pin 1 is the lower right pin and is marked on the board. Diamond Systems’ cable no. C-50-18 provides a standard 50-pin connector at each end and mates with this header.
4.
4.11 LCD Backlight Connector – J28 1 2 3 +12V Control Ground Table 11: J28 – LCD Backlight Connector Pinout Signal Name Control +12V, Ground Definition Output signal (from Athena) to allow power-down of backlight Power Supply for LCD Backlight assembly J28 provides the Backlight power and control for the optional LCD panel. See J24 (above) for details on the LCD data interface.
4.13 VGA Connector – J25 GREEN BLUE HSYNCH VSYNCH 1 3 5 7 2 4 6 8 RED Ground DDC-Data DDC-Clock Table 13: J25 – VGA Header Pinout Signal Name RED GREEN BLUE Ground DDC-CLOCK/DATA Definition RED signal (positive, 0.7Vpp into 75 Ohm load) GREEN signal (positive, 0.7Vpp into 75 Ohm load) BLUE signal (positive, 0.7Vpp into 75 Ohm load) Ground return Digital serial I/O signals used for monitor detection (DDC1 specification) J25 provides a connection for VGA monitors.
4.14 Audio I/O Connector – J15 1 2 3 4 5 6 7 8 9 10 LEFT Line Out RIGHT Line Out Audio Ground LEFT Line Input RIGHT Line Input Audio Ground Microphone Input Power Reference for Microphone NC (Key) Audio Ground Table 14: J15 – Audio I/O Connector Pinout Signal Name Line Out Line Input Microphone Input Definition Line Level output. These outputs are not capable of driving headphones. They must only be connected to high-impedance devices such as amplified speakers.
4.15 CD Input Connector – J30 J30 provides a connector for a PC-standard CD input cable. 1 2 3 4 LEFT CD Input Left Ground Right Ground RIGHT CD Input Table 15: J30 – CD Input Connector Pinout J30 provides the CD Audio Input to the AC97 Sound circuitry. The connector is an industrystandard CD-IN connector, as is common in most desktop Personal Computers. Note that the left and right grounds are decoupled, but are also tied together on-board. This input is intended for CD-input only (i.e.
5. JUMPER SETTINGS Refer to the Athena board drawing on page 8 for locations of the configuration items mentioned here. See page 23 for information on configuration J13 for the data acquisition circuit. 5.1 J10: System Configuration Jumper block J10 is used for configuration of IRQ levels, wait states, ATX power control, and CMOS RAM. Serial Port and A/D IRQ Settings COM3 may be set to IRQ4 or IRQ9. COM4 may be set to IRQ3 or IRQ15. The A/D circuit may be set to IRQ5 or IRQ4 if COM3 does not use it.
The different configurations for J10 are shown below. Each illustration shows only the jumper of interest. An asterisk (*) indicates the default setting. ATHENA CPU User Manual V1.
5.2 J13: Data Acquisition Circuit Configuration Jumper block J13 is used to configure the A/D and D/A circuits of the Athena. It is located on the left side of the board next to the data acquisition I/O pin header and is oriented vertically. The functions are shown below and are described in detail on the following page. The default settings are as shown: The various configurations are illustrated and described below.
Single-ended / Differential Inputs Athena can accept both single-ended and differential inputs. A single-ended input uses 2 wires, input and ground. The measured input voltage is the difference between these two wires. A differential input uses 3 wires: input +, input -, and ground. The measured input voltage is the difference between the + and - inputs.
6. SYSTEM FEATURES 6.1 System Resources The table below lists the default system resources utilized by the circuits on Athena.
6.2 COM Port / FPGA / Watchdog Control Registers A registers located at address 0x25F is used for the purposes of controlling the serial port, FPGA and watchdog features: Register Map Bit Assignments A blank bit in the write registers is unused. A blank bit in the read registers reads back as 0 or 1, unknown state.
6.3 Console Redirection to a Serial Port In many applications without a video card it may be necessary to obtain keyboard and monitor access to the CPU for configuration, file transfer, or other operations. Athena supports this operation by enabling keyboard input and character output onto a serial port (console redirection).
6.4 Flash Memory Athena contains a 2Mbyte 16-bit wide flash memory chip for storage of BIOS and other system configuration data. 6.5 Backup Battery Athena contains an integrated RTC / CMOS RAM backup battery. The battery is located adjacent to the PC/104 bus connector J1 (within the PC/104 outline). This battery has a capacity of 120mAH and will last over 3 years in power-off state. The on-board battery is activated for the first time during initial factory configuration and test.
7. BIOS 7.1 BIOS Settings Athena uses a BIOS from Phoenix Technologies modified to support the custom features of the Athena board. Some of these features are described here. To enter the BIOS during system startup (POST – power on self-test), press F2. Serial Ports -The address and interrupt settings for serial ports COM1 and COM2 may be modified. COM1 and COM2 address and interrupt settings are done in the BIOS, Advanced menu, I/O Device Configuration. See page 32 for details.
The Frame Buffer size can be increased for specific applications; just be aware that an increase in this memory size will result in a decrease in overall system memory available. The AGP rate affects internal video accesses and does not affect any external bus speeds. “Expansion Bus Performance” is an adjustment to allow an increase in ISA I/O Access speeds. For applications where ISA I/O accesses seem to be a limiting factor, this performance may be increased to “Accelerated”.
7.2 BIOS Console Redirection Settings For applications where the Video interfaces will not be used, the textual feedback typically sent to the monitor can be redirected to a COM PORT. In this manner, a system can be managed and booted without the need for any video connection.
8. SYSTEM I/O 8.1 Ethernet Athena includes a 10/100Mbps Ethernet connection using Cat-5 (100BaseT) wiring. The signals are provided on a 6-pin header (J4) on the right edge of the board. Diamond Systems’ cable no. 698002 mates with the header and provides a standard RJ-45 connector in panel-mount form for connecting to standard Cat5 network cables. 1 2 3 4 5 6 Common RXCommon RX+ TXTX+ Table 18: J11 – Ethernet Connector The Ethernet chip is the National Semiconductor DP83815 MacPhyter chip.
The settings of COM1 and COM2 may be changed in the system BIOS. Select the Advanced menu, then I/O Device Configuration. The base address and interrupt level may be modified on this page. The addresses of COM3 and COM4 are fixed. The interrupt (IRQ) settings for COM3 and COM4 are selected with J10. COM3 may use IRQ4 or IRQ9. COM4 may use IRQ3 or IRQ15. See page 20 for serial port IRQ jumper settings.
9. NOTES ON OPERATING SYSTEMS AND BOOTING PROCEDURES 9.1 Windows Operating Systems Installation Issues Installation of Windows operating systems ( Win98/2000/XP ) should follow the sequence below. If the sequence is not followed certain drivers might not work and may prevent the device from functioning properly under Windows. 1) Enable CD-ROM support in the BIOS. Change boot sequence in BIOS so system boots from CD-ROM first.
9.2 DOS Operating Systems Installation Issues Installation of DOS operating systems ( MS-DOS, FreeDOS, ROM-DOS ) should follow the sequence below. 1) Enable the following in BIOS: a. Floppy Drive detection. b. Legacy USB support. 2) Change BIOS boot sequence so system boots through USB floppy drive. 3) Insert DOS installation floppy disk into USB floppy drive and start/restart system. 4) Install various drivers needed. Note : For DOS Ethernet to work, in BIOS set “Operating System” to “other”.
10. DATA ACQUISITION CIRCUIT – I/O MAP AND REGISTER DESCRIPTIONS Models ATH400-128 and ATH660-128 contain a data acquisition subsystem consisting of A/D, D/A, digital I/O, and counter/timer features. This subsystem is equivalent to a complete add-on data acquisition module. The A/D section includes a 16-bit A/D converter, 16 input channels, and a 48-sample FIFO. Input ranges are programmable, and the maximum sampling rate is 100KHz. The D/A section includes 4 12-bit D/A channels.
10.1 Base Address The data acquisition circuitry on Athena occupies a block of 16 bytes in I/O memory space. The default address range for this block is 280h – 28Fh (base address 280). The data acquisition FPGA can be enabled/disabled in the BIOS under the Advanced menu. Scroll down to the “FPGA Mode:” option and select “Enabled” or “Disabled” accordingly. If the FPGA is disabled you will not be able to interact with the data acquisition circuit.
10.
10.3 Register Bit Definitions In these register definitions, a bit marked ‘X’ is an unused bit. All unused bits in readable registers read back as 0. Base + 0 Bit No. Name Write 7 Command Register 6 5 4 3 STRTAD RSTBRD RSTDA RSTFIFO CLRDMA 2 1 0 CLRT CLRD CLRA This register is used to perform various functions. The register bits are not data bits but instead command triggers. Each function is initiated by writing a 1 to a particular bit.
Base + 0 Read A/D LSB Bit No. 7 6 5 4 3 2 1 0 Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD7 - 0 A/D data bits 7 - 0; AD0 is the LSB; A/D data is an unsigned 16-bit value. The A/D value is derived by reading two bytes from Base + 0 and Base + 1 and applying the following formula: A/D value = (Base + 0 value) + (Base + 1 value) * 256 The value is interpreted as a twos complement 16-bit number ranging from –32768 to +32767.
Base + 2 Read/Write A/D Channel Register Bit No. 7 6 5 4 3 2 1 0 Name H3 H2 H1 H0 L3 L2 L1 L0 H3 – H0 High channel of channel scan range Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode. L3 - L0 Low channel of channel scan range Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode. The high channel must be greater than or equal to the low channel.
Base + 3 Write Analog Input Gain Bit No. 7 6 5 4 3 2 1 0 Name X X X X X SCANEN G1 G0 SCANEN 1 Scan mode enable: Each A/D trigger will cause the board to generate an A/D conversion on each channel in the range LOW – HIGH (the range is set with the channel register in Base + 2). The STS bit (read Base + 3 bit 7) stays high during the entire scan. 0 Each A/D trigger will cause the board to generate a single A/D conversion on the current channel.
Base + 3 Read Analog Input Status Bit No. 7 6 5 4 3 2 1 0 Name STS SD WAIT DACBSY OVF SCANEN G1 G0 STS A/D status. 1 = A/D conversion or scan in progress, 0 = A/D is idle. If SCANEN = 0 (single conversion mode), STS goes high when an A/D conversion is started and stays high until the conversion is finished. If SCANEN = 1 (scan mode enabled), STS stays high during the entire scan.
Base + 4 Bit No. Name CKSEL1 Read/Write 7 Interrupt / DMA / Counter Control 6 5 4 CKSEL1 CKFRQ1 CKFRQ0 ADCLK 3 2 1 0 DMAEN TINTE DINTE AINTE Clock source selection for counter/timer 1: 0 = internal oscillator, frequency selected by CLKFRQ1 1 = external clock input CLK1 (DIO C pins must be set for ctr/timer signals) CKFRQ1 Input frequency selection for counter/timer 1 when CKSEL1 = 1: 0 = 10MHz, 1 = 100KHz CKFRQ0 Input frequency selection for counter/timer 0.
Base + 6 Write DAC LSB Bit No. 7 6 5 4 3 2 1 0 Name DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7–0 Base + 6 D/A data bits 7 - 0; DA0 is the LSB. D/A data is an unsigned 12-bit value. This register must be written to before Base + 7, since writing to Base + 7 updates the DAC immediately. Read A/D Channel and FIFO Status Bit No. 7 6 5 4 3 2 1 0 Name 0 0 FD5 FD4 FD3 FD2 FD1 FD0 FD5–0 Current FIFO depth.
Base + 7 Write DAC MSB + Channel No. Bit No. 7 6 5 4 3 2 1 0 Name DACH1 DACH0 X X DA11 DA10 DA9 DA8 DACH1–0 D/A channel. The value written to Base + 6 and Base + 7 are written to the selected channel, and that channel is updated immediately. The update takes approximately 20 microseconds due to the DAC serial interface. DA11–8 Base + 7 D/A bits 11 - 8; DA11 is the MSB. D/A data is an unsigned 12-bit value. Read Analog Operation Status Bit No.
Base + 8 Read / Write Digital I/O Port A Bit No. 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 Base + 9 Read / Write Digital I/O Port B Bit No. 7 6 5 4 3 2 1 0 Name B7 B6 B5 B4 B3 B2 B1 B0 Base + 10 Read / Write Digital I/O Port C Bit No. 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 These 3 registers are used for digital I/O. The direction of each register is controlled by bits in the register below.
Base + 12 Read/Write Counter/Timer D7 - 0 Bit No. 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 This register is used for both Counter 0 and Counter 1. It is the LSB for both counters. When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s LSB register will be loaded with this value. When reading from this register, the LSB value of the most recent Latch command will be returned.
Base + 15 Write Counter/Timer Control Register Bit No. 7 6 5 4 3 2 1 0 Name CTRNO LATCH GTDIS GTEN CTDIS CTEN LOAD CLR This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any ONE of bits 6 – 0 to select the desired operation for that counter. The other bits and associated functions are not affected. Thus only one operation can be performed at a time. CTRNO Counter no.
Base + 15 Read FPGA Revision Code Bit No. 7 6 5 4 3 2 1 0 Name REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any ONE of bits 6 – 0 to select the desired operation for that counter. The other bits and associated functions are not affected. Thus only one operation can be performed at a time. REV7-0 Revision code, read as a 2-digit hex value, i.e. 0x20 = revision 2.
11. ANALOG-TO-DIGITAL INPUT RANGES AND RESOLUTION 11.1.1 OVERVIEW Athena uses a 16-bit A/D converter. The full range of numerical values for a 16-bit number is 0 65535. However the A/D converter uses twos complement notation, so the A/D value is interpreted as a signed integer ranging from –32768 to +32767. 16 The smallest change in input voltage that can be detected is 1/(2 ), or 1/65536, of the full-scale input range.
12. PERFORMING AN A/D CONVERSION This chapter describes the steps involved in performing an A/D conversion on a selected input channel using direct programming (not with the driver software). There are seven steps involved in performing an A/D conversion: 1. Select the input channel 2. Select the input range 3. Wait for analog input circuit to settle 4. Initiate an A/D conversion 5. Wait for the conversion to finish 6. Read the data from the board 7. Convert the numerical data to a meaningful value 12.
12.4 Perform an A/D conversion on the current channel After the above steps are completed, start the A/D conversion by writing to Base + 0. This write operation only triggers the A/D if AINTE = 0 (interrupts are disabled). When AINTE = 1, the A/D can only be triggered by the on-board counter/timer or an external signal. This protects against accidental triggering by software during a long-running interrupt-based acquisition process. outp(base,0x80); 12.
12.7 Convert the numerical data to a meaningful value Once you have the A/D value, you need to convert it to a meaningful value. The first step is to convert it back to the actual measured voltage. Afterwards you may need to convert the voltage to some other engineering units (for example, the voltage may come from a temperature sensor, and then you would need to convert the voltage to the corresponding temperature according to the temperature sensor’s characteristics).
13. A/D SCAN, INTERRUPT, AND FIFO OPERATION The control bits SCANEN (scan enable) and AINTE (A/D interrupt enable) in conjunction with the FIFO determine the behavior of the board during A/D conversions and interrupts. At the end of an AD conversion, the 16-bit A/D data is latched into the 8-bit FIFO in an interleaved fashion, first LSB, then MSB. A/D Data is read out of the FIFO with 2 read operations, first Base + 0 (LSB) and then Base + 1 (MSB).
13.1 Athena A/D Operating Modes The following control bits and values are referenced in the descriptions in the table below. AINTE Base + 4 bit 0 SCANEN Base + 3 bit 2 FIFO threshold Base + 5 bits 5-0 STS Base + 3 bit 7 LOW, HIGH 4-bit channel nos. in Base + 2 ADCLK Base + 4 bit 4 AINTE SCANEN Operation 0 0 - Single A/D conversions are triggered by write to B+0. - STS stays high during the A/D conversion. - No interrupt occurs.
14. ANALOG OUTPUT RANGES AND RESOLUTION 14.1 Description Athena uses a 4-channel 12-bit D/A converter (DAC) to provide 4 analog outputs. A 12-bit DAC can generate output voltages with the precision of a 12-bit binary number. The maximum value of 12 a 12-bit binary number is 2 - 1, or 4095, so the full range of numerical values that the DACs support is 0 - 4095.
14.4 D/A Conversion Formulas and Tables The formulas below explain how to convert between D/A codes and output voltages. D/A Conversion Formulas for Unipolar Output Ranges Output voltage = (D/A code / 4096) * Reference voltage D/A code = (Output voltage / Reference voltage) * 4096 Example: Output range in unipolar mode = 0 – 10V Full-scale range = 10V – 0V = 10V Desired output voltage = 2.000V D/A code = 2.000V / 10V * 4096 = 819.2 => 819 Note the output code is always an integer.
D/A Conversion Formulas for Bipolar Output Ranges Output voltage = ((D/A code – 2048) / 2048) * Output reference D/A code = (Output voltage / Output reference) * 2048 + 2048 Example: Output range in bipolar mode = ±10V Full-scale range = 10V – (-10V) = 20V Desired output voltage = 2.000V D/A code = 2V / 10V * 2048 + 2048 = 2457.6 => 2458 For the bipolar output range ±10V, 1 LSB = 1/4096 * 20V, or 4.88mV.
15. GENERATING AN ANALOG OUTPUT This chapter describes the steps involved in generating an analog output (also called performing a D/A conversion) on a selected output channel using direct programming (not with the driver software). There are three steps involved in performing a D/A conversion: 1. Compute the D/A code for the desired output voltage 2. Write the value to the selected output channel 3. Wait for the D/A to update 15.
16. ANALOG CIRCUIT CALIBRATION Calibration applies only to boards with the analog I/O circuit. The analog I/O circuit is calibrated during production test prior to shipment. Over time the circuit may drift slightly. If calibration is desired follow the procedure below. For analog I/O circuit configuration see page 23. Four adjustments are possible: ♦ A/D bipolar offset ♦ A/D unipolar offset ♦ A/D full-scale ♦ D/A full-scale No adjustment for D/A offset is possible. 16.
17. DIGITAL I/O OPERATION Athena contains 24 digital I/O lines organized as three 8-bit I/O ports, A, B, and C. The direction for each port is programmable, and port C is further divided into two 4-bit halves, each with independent direction. The ports are accessed at registers Base + 8 through Base + 10 respectively, and the direction register is at Base + 11.
18. COUNTER/TIMER OPERATION Athena contains two counter/timers that provide various timing functions on the board for A/D timing and user functions. These counters are controlled with registers in the on-board data acquisition controller FPGA. See pages 44 and 49 for information on the counter/timer control register bits and how to perform various functions using these counters. 18.
18.3 Command Sequences Diamond Systems provides driver software to control the counter/timers on Athena. The information here is intended as a guide for programmers writing their own code in place of the driver and also to give a better understanding of the counter/timer operation. The counter control register is shown below. Base + 15 Write Counter/Timer Control Register Bit No.
Reading a counter a. Latch the counter: Counter 0 outp(base+15,0x40); Counter 1 outp(base+15,0xC0); b. Read the data: The value is returned in 3 bytes, low, middle, and high (2 bytes for counter 1) Counter 0 low=inp(base+12); middle=inp(base+13); high=inp(base+14); c.
19. WATCHDOG TIMER PROGRAMMING 19.1 Watchdog Timer Athena contains a watchdog timer circuit consisting of one programmable timer, WDT. The input to the circuit is WDI, and the output is WDO. Both signals appear on the watchdog connector J6. WDI may be triggered in hardware or in software. A special “early” version of WDO may be output on the WDO pin. When this signal is connected to WDI, the watchdog circuit will be retriggered automatically. The duration of the timer is user-programmable.
19.2 Watchdog Timer Register Details 0x25C Write Bit No. 7 WDT Trigger Register 6 5 0x25C 3 2 1 0 WDTRIG Name WDTRIG 4 Writing a 1 to this bit triggers an immediate software reload of the WDT watchdog timer. Read WDT Trigger Register This register does not read back. 0x25D Write Bit No. 7 6 5 4 Name WDT3 WDT2 WDT1 WDT0 WDT0-3 0x25D WDT Counter Register 3 2 1 0 Writing to bits WDT0-3 loads WDT with the 4-bit counter value. Use this register to set the WDT countdown period.
0x25E Write Bit No. Name WDIEN 7 WDT Control Register 6 5 4 3 2 1 0 WDIEN WDOEN WDSMI WDEDGE 0 = Disable edges on the WDI pin retriggering WDT. 1 = Enable egdes on the WDI pin retriggering WDT. WDOEN 0 = Disable edge on WDO pin when WDT reaches 1. 1 = Enable edge on WDO pin when WDT reaches 1. WDSMI 0 = Disable SMI signal when WDT reaches 0. 1 = Enable SMI signal when WDT reaches 0. WDEDGE 0 = Falling edge on WDI retriggers WDT when WDIEN = 1.
19.3 Example : Watchdog Timer With Software Trigger Software trigger relies on a thread of execution to constantly trigger WDT. If the thread is ever halted, WDT will reach zero and initiate the reset sequence. In this example we will set the watchdog timer to a countdown period of 2.175 seconds.
20. DATA ACQUISITION SPECIFICATIONS These specifications apply to units with Data Acquisition Only Analog Inputs No. of inputs A/D resolution Input ranges 8 differential or 16 single-ended (user selectable) 16 bits (1/65,536 of full scale) Input bias current Bipolar: ±10V, ±5V, ±2.5V, ±1.25V Unipolar: 0-8.3V, 0-5V, 0-2.
21. FLASHDISK MODULE Athena is designed to accommodate an optional flashdisk module. This module contains 32MB to 128MB of solid state non-volatile memory that operates like an IDE drive without requiring any additional driver software support. Model FD-32 FD-64 FD-96 FD-128 Capacity 32MB 64MB 96MB 128MB 21.1 Installing the Flashdisk Module The flashdisk module installs directly on the IDE connector J16 and is held down with a spacer and two screws onto a mounting hole on the board.
22. FLASH DISK PROGRAMMER BOARD The Flash Disk Programmer Board accessory model no. ACC-IDEEXT may be used for several purposes. Its primary purpose is to enable the simultaneous connection of both a flashdisk module and a standard IDE hard drive or CD-ROM drive to allow file transfers to/from the flashdisk. This operation is normally done at system setup. The board can also be used to enable the simultaneous connection of two drives to the CPU.
23. I/O CABLES Diamond Systems offers a cable kit no. C-ATH-KIT with 10 cables to connect to all I/O headers on the board. Some cables are also available separately. The mating cable for each I/O connector is listed in Chapter 4. Figure 2 : Cable Kit C-ATH-KIT Photo No. Cable No.
24. QUICK START GUIDE This section will describe the steps necessary to get your Athena up and running. It is assumed that you have also purchased the Athena Development Kit. This kit includes all cables described on on page 73, a power supply, USB floppy drive, mounting hardware, IDE flashdisk and the flashdisk programmer board. More details about the development kit can be found here: http://www.diamondsystems.com/products/athena#dk 24.
24.3 Booting into MS-DOS, FreeDOS or ROM-DOS This section describes how to boot into a DOS-based operating system via a bootable floppy disk. 1) Plug the USB floppy drive into one of the USB terminals of cable 698012 (see step 7.) 2) Insert your DOS-based boot disk into the USB floppy drive. 3) Connect the power supply to the wall (to provide power to Athena) 4) At this point the Athena will boot and you should see the BIOS power-on self test (POST.) Press F2 at this screen to enter BIOS configuration.
