Instruction manual

FUNCTIONAL DESCRIPTION
information.
It also allows the port circuit microprocessor to inform the on-board
microprocessor of various port circuit status information.
The DUCK and TRIC interface I-channel information between the port circuit and the
remote data module. The microprocessor controls the operation of the DUCK and
the TRIC by programming their internal registers. The DUCK and TRIC together
recreate the clock and serial data stream from the remote data module, and process
an on-board clock and serial data stream for delivery to the remote data module.
Control information, handshaking, and RS-232 control leads is passed between the
port circuit microprocessor and the remote data module by the TRIC.
The USART interfaces the serial data stream of the DUCK to the conversion
microprocessor.
The USART can be programmed by the microprocessor to operate
synchronously or asynchronously. The USART also does the following tasks for the
port circuit microprocessor:
— Appends start and stop bits to parallel data received from the microprocessor
in the asynchronous mode
— Converts serial data received from the DUCK to parallel data
— Buffers data in both directions
— Detects and generates break characters.
The DSP provides modem emulation. It interfaces the port circuit signal and the
remote modem. The microprocessor directs the DSP to execute one of many
programs.
The DSP produces data, carrier detection, and timing information for the
port circuit microprocessor.
DS1 Interface (TN767)
The DS1 Interface Circuit Pack provides connection capability to a 1.544 Mbps DS1 facility.
This DS1 facility is able to provide a communication link for 24 separate and independent
trunks. Each trunk provides a 64 kbps data transmission service for a DS1 Voice Grade tie
trunk. The circuit pack can also provide bit-oriented signaling on a per trunk basis.
Supported trunks include; automatic, immediate-start, delay-dial, and release-link trunks. The
circuit pack performs robbed-bit signaling using CO, TIE, DID, or OPS signaling protocol in
any remaining ports on a per port basis. The following lead appearances are provided on
the circuit pack: LBACK2, LBACK1, LO, LO (high), LI, LI (high).
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