Instruction manual

FUNCTIONAL DESCRIPTION
● On-Board Microprocessor With External RAM
This circuit functions the same as the microprocessor in the common circuitry for the
intelligent port circuits.
In addition, it tells the dual-port RAM in the time slot table
circuit the appropriate time slots in which to place a tone. The external RAM also
has work space for complex tones (i.e., those tones that vary with time).
● Clock Circuit
The clock circuit consists of a 20.48-MHz oscillator, various dividers, and shift
registers. The clock circuit runs independently from the rest of the Service Circuit
circuitry. The clock circuits start running when the circuit pack is first powered up
and is not controlled by the on-board microprocessor.
The output of the 20.48-MHz oscillator is fed to the clock divider. The divider divides
by 10, 2560, and 128. These circuits produce the 2.048-MHz, 8-kHz, and 160-kHz
clock signals, respectively.
The clock generator feeds these signals to the clock
driver/receiver bus buffer and the tone clock.
The tone clock uses these signals to
synchronize the counters in the tone generator and time slot table circuits with the
TDM bus.
● Tone Generator
The tone generator consists of a digital signal processor (DSP), a counter, and a
dual-port tone RAM. The DSP operates at 10 MHz and produces 24 different tones.
The dual-port tone RAM stores these tones in 24 different addresses. The counter
under control of the tone clock causes the DSP to transmit one sample of each tone
every 8-kHz. The counter is synchronized to the TDM bus and is offset to provide
delay needed for access time.
● Time Slot Table and Counter
The time slot table consists of a dual-port time slot table RAM and a counter. The
dual-port RAM (DPRAM) contains 256 different addresses. These addresses
correspond to the time slots on the TDM bus. The counter sequences through the
time slot table addresses in the dual-port RAM and causes the proper tone(s) to be
output by the dual-port tone RAM on TDM bus time slots.
● Tone Detector Ports
The Service Circuit CP provides four Dual Tone Multifrequency (DTMF) detector port
circuit interfaces via the TDM bus. Each port circuit is connected to an NPE serial
input and output.
Ports 0, 1, 2, and 3 are DTMF tone detectors with NPE loop-
around paths.
The four port circuits contain a DSP, NPE to DSP interface circuitry, a DSP restart
circuit, and an interrupt generator. One DSP implements two tone receivers.
The TDM bus signals are connected to the DSP in serial form from the NPEs by the
DSP interface circuit. The DSP controls the output clocking of the NPE. The system
framing signal is synchronized and connects to the DSP.
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