User's Manual

Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 57
between the two data lanes and the clock. There are no special delay-matching requirements between
lanes in opposite directions.
Table 9–3 CNVio recommended parameters
Parameter Value Comment
Differential pair length
matching:
0.02UI
For 1280M: <80 mil
This parameters may effect EMI and RFI
Characteristic impedance 100 ohm differential 50 ohm to ground for each trace
Maximum length 10 inch 9 inch from M.2 connector pins to SoC pins
Maximum resistance 5 ohm 50 ohm to ground for each trace
Shielding Berried microstrip (Stripline) Recommended for minimizing EMI/RFI
Delay matching between pairs of
the same direction
Better than 80 mil Including the 2 lanes and the clock in every
direction
Vias Minimize usage Recommended to avoid Via connections as
much as possible and follow differential
BER 1E-12 Standard PHY bit error rate for a CNVio lane
RGI and BRI signals
These are GPIO signals (1.8V) running between the SoC and the RF companion module. The BRI and
RGI signals share the same traces as UART signals (for discrete). Since the UART baud rate is
expected to be lower than the BRI/RGI toggle rate, it can be assumed that the BRI/RGI sets the
requirements for this bus. BRI and RGI are two bi-directional busses. No special control impedance is
needed. The BRI and RGI packets are protected by error-correction coding and with standard routing
and signal integrity practices applied, no errors are expected to be noticed on the busses.
38.4M reference clock signal
Ref Clock is a 38.4M clock signal which is generated by the RF companion module and sent to the SoC.
This clock can be used as the SoC main clock (in clock sharing configuration) or as the Pulsar clock (in
non-clock sharing configuration). When using the latter option, the SoC should have another clock for
its operation, but Pulsar (within the SoC) will always get the 38.4M clock coming from the Companion
RF module.
The clock signal is a 1V nominal, 10Kohm typical resistive load with 35pF load capacitance.
It is recommended to route the clock with special care while maintaining clock routing practices,
preferably as a microstrip to minimize EMI/RFI and susceptibility to noise.