User's Manual

Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
External Product Specification (EPS) April 2017
56 Intel Confidential Document Number: 567240–1.0
I/F Signals PU/PD Guideline Rationale
BRI_RSP / Rx PU Intel SoC with CNVi support have
internal PU/PD as needed.
RGI_DT / Tx Intel SoC with CNVi support have
internal PU/PD as needed.
BT UART WAKE# PU Open drain, required by M.2
W_Disable# PU Required by Intel platform design
guidelines
PCIe PEWAKE# PU Open drain, required by M.2
CLKREQ# PU Open drain, required by M.2
PERST# PD Required by Intel platform design
guidelines
Other PCIe
signals
None PCIe spec
38.4 Ref clock RefCLK PD
The OEM must avoid using PU/PD when not needed or when required not to be used. If this rule is not
followed, it will result in a back-bias condition, where the IO is getting voltage before the device side is
ready for it.
9.1.8 IO connection scenarios and best practices
The motherboard designer should address the following requirements for the sake of avoiding failsafe
problems, reducing unneeded leakage, and for following best-practice design rules:
 Level-shifter back-bias prevention
– Level shifter shall not set value in A side when not getting voltage in B side.
 Rationale: Prevent back-bias and wrong logic conditions.
– Level shifters shall be back-bias protected.
 Rationale: The level shifter is often supplied with a different supply than the IO
connected to it. During ramp up/down states there might be a back-bias scenario.
9.1.9 I/F specific guidelines
CNVio signals
The CNVio signals connect the RF companion module and the SoC. They are used as the main data
bus for Wi-Fi to transfer data between the Pulsar and the RF companion chip. The CNVio signals are
PHYsically similar to the MiPi DPHY standard, but have a different (and Intel-proprietary) protocol.
Since the PHYsical layer of the
CNVio is similar to a standard, the user should follow the MiPi DPHY
routing signal requirements. These are well documented in the MiPi DPHY standard specification. (See
Chapter 7 of the MiPi DPHY standard: “Interconnect and Lane Configuration.”)
The
CNVio bus is source synchronous, and runs at a clock rate of 1280Mhz. Each lane has data
carried over a differential pair, and each direction may have multiple lanes and a single clock, driven
by the source.
Routing
The routes of the two traces of each lane must match as much as possible. Moreover, since the CNVio
uses one clock signal for multiple lanes in each direction, there should also be good delay matching