User's Manual

Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
External Product Specification (EPS) April 2017
50 Intel Confidential Document Number: 567240–1.0
NFC I/F, and A4WP+Ref clock
In the Hybrid Key E scheme, only one of these four signals is used. This REFCLK0 signal connects the
reference clock (single ended, 1V p-p, 38.4MHz) from the RF companion to the SoC. The remaining
three signals are not used.
Non-shared M.2 socket pins
Some pins on the M.2 connector are not shared, meaning they are not used for any CNVi function. The
functions of these pins can still be impacted by the Hybrid key E scheme as will be described here.
PEWake1#, CLKREQ1#, PERST1#
These are three control signals used by the PCIe-1 bus in standard M.2 cards. Although these signals
are not shared with any other function, they have no usage in a Hybrid Key E scheme design. This is
because the PCIe-1 bus by itself is not usable. (See “PCIe-1/CNVio,” above.)
PCIe-0 Bus
This consists of six signals (three differential pairs) used for PCIe data to and from the SoC, and a
single pair used for the PCIe bus clock. In a CNVi RF companion, these signals are left unused. In a
discrete module, these signals are being used as the Wi-Fi bus interface.
W_DISABLE1#, W_DISABLE2#
These are used for Wi-Fi and BT RF-KILL control, respectively. (Asserting these signals shuts off the
RF transmission or the relevant core.) The functions of these signals are the same for Hybrid Key E,
and therefore they are not affected by this scheme.
PEWake0#, CLKREQ0#, PERST0#
These are three control signals used by the PCIe-0 bus in standard M.2 cards. They should be routed
to SoC pins that are assigned to GPIOs in Discrete or Combo modes.
Coex UART interface
This interface consists of three signals (two UART bus signals and one GPIO). They are used for
Wi-Fi/BT-LTE coexistence signaling in the M.2 standard definition. Since these pins are left unused in
the RF companion, they can still be used with a discrete M.2 card even when designing with the Hybrid
Key E scheme. In platforms that are designed to support a WWAN modem and Hybrid Key E, there
should be three pins connected to each signal, to allow the modem to connect to the M.2 pin (in the
discrete connectivity case) or to the PCH (in the CNVi case).
CLINK interface
This interface consists of three signals (clock, data and reset). This bus in an Intel-proprietary bus.
Since these pins are left unused in the RF companion, they can still be used with a discrete M.2 card,
even when designing with the Hybrid Key E scheme.
LED1, LED2
These are optional pins that are assigned to drive LEDs on the platform in the standard M.2 cards.
They are used for the same function when using CNVi, and therefore are not affected by the Hybrid
Key E scheme.
USB bus
The standard M.2 defines two pins for a differential USB bus. This bus has no usage in the RF
companion. When using a standard M.2 discrete card, the pins will have the standard functionality and
are not affected by the Hybrid Key E scheme.
The different connectivity interfaces as used by a discrete connectivity (Standard M.2, Intel
connectivity, or TPV) and CNVi RF companion card are summarized in Table 9–1. The table also points
to the different restrictions posed by the use of a Hybrid Key E socket design on the motherboard.