User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Electrical Specifications
Intel
®
Wireless-AC 9560 (Jefferson Peak)
External Product Specification (EPS) April 2017
24 Intel Confidential Document Number: 567240–1.0
NOTES:
1. I2C max speed will be 1MHz (Fast plus Mode). I2C SDA & SCL I/Os must comply with 120ns
max rise/fall time. I/O are protected against back-bias up to 1.8V and can withstand I/O
voltage when the power supply is off.
2. I/O are protected against back-bias up to 1.98V and can withstand I/O voltage when the power
supply is off.
3. Input is 3.6V tolerant. I/O are protected against back-bias up to 3.6V and can withstand I/O
voltage when the power supply is off.
4. I/O are protected against back-bias up to 1.98V and can withstand I/O voltage when the power
supply is off.
5. The D-PHY I/O pins must comply with the DC electrical specifications in “MIPI Alliance
Specification for D-PHY Rev1.1.” Specifically, the D-PHY JfP transmitter (JfP to Pulsar) DC
characteristics are found in Section 9.1, Table 16. The D-PHY JfP receiver (Pulsar to JfP) DC
characteristics are found in Section 9.2, Table 20.
3.3 Peak current consumption
Table 3-4 Peak current consumption
Name Description Value [mA] Notes
Peak current
Peak current from 3.3 V supply 1360
3.4 M.2 power and ripple limits
The supply voltage rise should be continuous and with a max rise time of 10mSec (0 V to 3.3 V). It
should not have any glitches or steps. Figure 3–1 shows examples of wrongful and correct power up
schemes.
Figure 3–1 Power supply rise flow
X X √
3.4.1 Power supply ripples
There must not be any glitches on the power supply that dip more 0.3 V. Any glitch that is higher than
0.3V may be interpreted by the module as a power-on reset, which will cause the module to lose
stored data and reboot.
During platform low-power modes, such as S3 (stand-by state), glitches will lead to connection failure.