User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Electrical Specifications
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 17
Pin
#
Pin Name
Platform
Pinout
Pin Name
Module Pinout
Direction
w/respect
to JfP
Module
JfP
Voltage on
Module Side
Connection on Platform/Usage
Shall be connected to PCIe PCIe for
supporting discrete module.
56 W_DISABLE1# W_DISABLE1# I 3.3 V
JfP also supports 1.8 V electrical levels on
this signal
57 GND GND
58 I2C DATA/
A4WP_I2C_DA
TA
NC 1.8 V
Not used by Jefferson Peak.
59 WT_D1N WT_D1N CNVio PHY
CNVio bus TX lane 1
60 I2C CLK/
A4WP_I2C_CL
K
NC 1.8 V
Not used by Jefferson Peak.
61 WT_D1P WT_D1P I CNVio PHY
CNVio bus TX lane 1
62 ALERT#/
A4WP_IRQ#
NC 1.8 V
Not used by Jefferson Peak
63 GND GND
64 REFCLK0 REFCLK0 O 1 V
38.4MHz clock from the JfP Module to the
SoC
65 WT_D0N WT_D0N I CNVio PHY
CNVio bus TX lane 0
66 PERST1# NC
Not used by Jefferson Peak
67 WT_D0P WT_D0P I CNVio PHY
CNVio bus TX lane 0
68 CLKREQ1# NC
Not used by Jefferson Peak
69 GND GND
70 UIM_POWER_
SRC/GPIO1/
PEWAKE1#
NA
Not used by Jefferson Peak
71 WT_CLKN WT_ CLKN I CNVio PHY
CNVio bus TX clock
72 3.3 V 3.3 V
3.3 V Supply
73 WT_ CLKP WT_ CLKP I CNVio PHY
CNVio bus TX clock
74 3.3 V 3.3 V
3.3 V Supply
75 GND GND
Table 3-2 1216-platform module pinout (M.2 revision for 2015)
Pin # Pin name Function when CNVi
is used
Function when Standard
(discrete) M.2 is used
Comments
1 UIM_POWER_SRC/GPIO1 Not used UIM_POWER_SRC/GPIO1
2 UIM_POWER_SNK Not used UIM_POWER_SNK
3 UIM_SWP Not used UIM_SWP
4 3.3V 3.3V 3.3V
5 3.3V 3.3V 3.3V