User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Electrical Specifications
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 15
Pin
#
Pin Name
Platform
Pinout
Pin Name
Module Pinout
Direction
w/respect
to JfP
Module
JfP
Voltage on
Module Side
Connection on Platform/Usage
16 LED2# LED2# O OD
BT LED
17 WGR_D0P WGR_D0P O CNVio PHY
CNVio bus RX lane 0
18 GND LNA_EN
This a special purpose test pin of the JfP
module. Should be connected to Ground
on the platform.
19 GND GND
20 UART WAKE# NC O 3.3 V
Not used by Jefferson Peak
Optional PCM interface for supporting
discrete module
21 WGR_CLKN WGR_ CLKN O CNVio PHY
CNVio bus RX clock
22 UART
RXD/BRI_RSP
BRI_RSP O 1.8 V
BRI bus RX
Optional PCM interface for supporting
discrete module
23 WGR_CLKP WGR_ CLKP O CNVio PHY
CNVio bus RX clock
24 Connector Key Module Key
25 Connector Key Module Key
26 Connector Key Module Key
27 Connector Key Module Key
28 Connector Key Module Key
29 Connector Key Module Key
30 Connector Key Module Key
31 Connector Key Module Key
32 UART
TXD/RGI_DT
RGI_DT I 1.8 V
BRI bus TX
Optional PCM interface for supporting
discrete module
33 GND GND
34 UART
CTS/RGI_RSP
RGI_RSP O 1.8 V
RGI bus RX
Optional PCM interface for supporting
discrete module
35 PETp0 NC PCIe PHY
Not used by Jefferson Peak
Shall be connected to PCIe for supporting
discrete module
36 UART
RTS/BRI_DT
BRI_DT I 1.8 V
BRI bus TX
37 PETn0 NC PCIe PHY
Not used by Jefferson Peak
Shall be connected to PCIe for supporting
discrete module
38 CLINK RESET NC
Not used by Jefferson Peak
Optional CLINK interface for supporting
discrete module
39 GND GND