User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Electrical Specifications
Intel
®
Wireless-AC 9560 (Jefferson Peak)
External Product Specification (EPS) April 2017
14 Intel Confidential Document Number: 567240–1.0
3 Electrical Specifications
This section provides information about the electrical specifications of the Jefferson Peak module. The
specifications cover the module hardware interface signals.
3.1 2230 and 1216 form factor pinouts
There are two pinout lists, one for the platform side, and one for the module side. Note that some
signals are crossed (such as UART Rx on platform side is connected to TX on the module side).
Note: The 2230 module pinout is based on the Hybrid Key E scheme. The Hybrid Key E is an
Intel-proprietary scheme, which is based on the mechanical and electrical specifications of
the PCIe M.2 Electromechanical Spec, modified by changes to the pinout in order to
support Intel’s Integrated Connectivity (CNVi).
Table 3-1 Hybrid Key E 2230-platform module pinout
Pin
#
Pin Name
Platform
Pinout
Pin Name
Module Pinout
Direction
w/respect
to JfP
Module
JfP
Voltage on
Module Side
Connection on Platform/Usage
1 GND GND
2 3.3 V 3.3 V 3.3 V
3.3 V Supply
3 USB_D+ NC IO 3.3 V
Not used by Jefferson Peak
Shall be connected to USB for supporting
discrete module
4 3.3 V 3.3 V 3.3 V
3.3 V Supply
5 USB_D- NC IO 3.3 V
Not used by Jefferson Peak
Shall be connected to USB for supporting
discrete module
6 LED1# LED1# O OD
Wi-Fi LED
7 GND GND
8 PCM_CLK/I2S
SCK
NC IO 1.8 V
Not used by Jefferson Peak
Optional PCM interface for supporting
discrete module
9 WGR_D1N WGR_D1N O CNVio PHY
CNVio bus RX lane 1
10 PCM_SYNC/I2S
WS/RF_RESET
_B
RF_RESET_B I 1.8 V
Jefferson peak RF (active low)
Optional PCM interface for supporting
discrete module
11 WGR_D1P WGR_D1P O CNVio PHY
CNVio bus RX lane 1
12 PCM_IN/I2S
SD_IN
NC O 1.8 V
Not used by Jefferson Peak
Optional PCM interface for supporting
discrete module
13 GND GND
14 PCM_OUT/I2S
SD_OUT/CLKR
EQ0
CLKREQ0 I 1.8 V
Clock request for the 38.4MHz clock (CNVi
reference clock)
Optional PCM interface for supporting
discrete module
15 WGR_D0N WGR_D0N O CNVio PHY
CNVio bus RX lane 0