User's Manual

Product Architecture
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 13
The Jefferson Peak M.2 module interfaces the platform and the SoC through a proprietary interface for
CNVi. This interface connects between the JfP module and the SoC and between the JfP module and
the platform. A high-level description of the interface is shown in Figure 2–2.
Power supply
The Jefferson peak module is powered by a 3.3V supply connected to the dedicated power pins on the
M.2 module connector. Proper decoupling capacitors are required to be placed close to the
module/socket pins. See more details in Section 1.1.1.
32KHz clock
The Jefferson Peak module requires a slow (low power) clock to be supplied at the dedicated M.2 pins.
This clock is normally generated by the SoC and routed between the SoC and the M.2 module. The
clock rate is 32KHz and the signal is a standard logic level (either 3.3V or 1.8V can be used).
BRI/RGI
These are two serial asynchronous busses used for BT traffic (BRI) and for control data (RGI). Each
bus has one signal per direction. The BRI and RGI busses do not require any clock to be sent with the
data lines as the clock at the receiving end of the bus is extracted from the data itself. The BRI and
RGI toggle at 76.4Mbouds each (full duplex). The signals are standard 1.8V logic level. The BRI and
RGI do not need any pull-up resistors on the board.
CNVio
The CNVio signals connect the JfP module and the SoC. They are used as the main data bus for Wi-Fi,
to transfer data between the Pulsar and the RF companion chip. The CNVio signals are PHYsically
similar to the MIPI DPHY standard, but have a different (and Intel-proprietary) protocol.
The CNVio bus has two data lanes and one clock for each direction. Both data and clock signals are
differential, 100-Ohm signals. The total number of signals for the interface is 12 (6 pairs, 3 per
direction). These signals should be routed as differential, controlled impedance traces. Due to the
sensitivity of the CNVio bus to signal impairments, RF layout techniques and good length matching
shall be used. Section 9.1.9.1 contains specific design guidelines for the CNVio routing.
Reference clock (38.4MHz)
This is the main clock used for both Pulsar (the MAC part which is inside the SoC) and Jefferson Peak.
The clock is driven by the JfP output clock buffer at voltage levels of 1V (pk-pk). This clock shall be
routed from JfP to the SoC with special care to minimize clock jitter. Section 9.1.9.3 contains specific
design guidelines for the reference clock routing.
Reset and Clock Request
The Reset and Clock Request signals are automatically driven by the SoC to control the operation of
the Companion RF and minimize system power consumption. The SoC uses the Reset only at initial
power up. The Clock Request signal is used to change the Jefferson Peak power modes between high-
power clock and low-power clock (per the system power states).
LEDs
Jefferson Peak M.2 module supports driving two LEDs to indicate wireless activity. These pins have
open-drain buffers which sinks current (logical zero) when the LED is turned on.
RF-KILL
Jefferson Peak M.2 module SKUs support wireless disable (RF-KILL) command through the two RF-
KILL pins for turning off Wi-Fi and BT respectively. These pins can be connected to a platform switch
or SoC GPIOs.