User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Product Architecture
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 11
2 Product Architecture
2.1 Integrated Connectivity concept
2.1.1 MAC-PHY split
Integrated Connectivity (CNVi) is a new architecture for wireless connectivity devices. The concept of
CNVi is to move a large part of the functional content of the connectivity chip from the radio chip into
the Intel SoC. As a result, a large portion of the chip logic and memory resources is moved out of the
radio chip while reducing the platform’s bill of material (BOM) size and cost.
In the CNVi architecture, the MAC components of the Wi-Fi and Bluetooth cores, including processors,
logic, and memory, are relocated from the radio chip into the SoC chip. Signal processing, analog and
RF functions stay in the radio chip, which is called a Companion RF (CRF) chip or module in CNVi
terminology.
The part of the connectivity chip that is ported into the SoC is called Pulsar. Pulsar interfaces with the
rest of the SoC functions through SoC-internal interfaces and busses, and does not require any
external host interfaces at the platform level. On the other hand, interfacing Pulsar with the CRF
module does require platform signals to be routed between the SoC and the CRF module. The CNVi
architecture and the MAC-PHY split is shown in Figure 2–1.
The integrated connectivity architecture places the MAC component of the Wi-Fi and BT cores inside
the SoC. As a result, the host interfaces of Wi-Fi and BT are no longer part of the M.2 module, which is
a Companion RF module. These host interfaces reside in the SoC and are not exposed to the platform.
Figure 2–1 CNVi architecture
SOC
Pulsar
CRF Module
WiFi/BT
PHY/RF
M.2 pins
CNVio
PCH resources
(Power, I/O Chassis)
Platform power
Platform power
GPIOs (RGI/BRI), clocks
2.1.2 SoC and Companion RF compatibility
In order to use the integrated connectivity architecture, the platform needs to include both an SoC
and a connectivity device which supports CNVi. This means that the SoC needs to have the Pulsar
block integrated, and a Companion RF module should be used in the design. The Jefferson Peak
Companion RF module can support the following Intel SoC devices, which include Pulsar:
• Cannon Lake PCH-LP
• Cannon Lake PCH-H
• Gemini Lake