User Manual

32
ROG STRIX X299-E GAMING BIOS Manual
Initial PCIE Frequency
Conguration options: [Auto] [80] - [200]
PCIE/DMI Amplitude
This item allows you to set the signal magnitude of the reference PCIE/DMI CLK
supplied to the processor. Higher values may improve overclocking stability.
Conguration options: [Auto] [700mV] [800mV] [1000mV] [1500mV]
PCIE/DMI Spread Spectrum
Conguration options: [Auto] [Disabled] [Enabled]
PCIE/DMI Frequency Slew Rate
Conguration options: [Auto] [Ultra Fast] [Fast] [Normal] [Slow]
PCIE/DMI Slew Rate
This item allows you to set the speed at which each clock rises and falls.
Conguration options: [Auto] [1.5V/ns] [2.5V/ns] [3.5V/ns] [4.5V/ns]
VTTDDR Voltage(CHC, CHD)
This item allows you to congure the termination voltage for memory channel C and
channel D. Setting is at Auto, scales this setting at 50% of the applied DRAM voltage.
Use the <+> or <-> to adjust the value. The values have an interval of 0.00625V.
Conguration options: [Auto] [0.500] - [1.300]
VPPDDR Voltage(CHC, CHD)
This item allows you to congure the auxiliary power supply to the DDR4 DRAM
Modules on the right. Use the <+> or <-> to adjust the value. The values have an
interval of 0.005V.
Conguration options: [Auto] [1.865] - [3.135]
DMI Voltage
Conguration options: [Auto] [0.30000] - [2.10000]
Core PLL Voltage
The congurations for this option differs when LN2 Mode is enabled or disabled.
LN2 Disabled: [Auto] [0.700] - [1.700]
LN2 Enabled: [Auto] [0.700] - [2.400]
Internal PLL Voltage
Conguration options: [Auto] [0.900] - [1.845]
PLL Bandwidth
Select Level 6 to Level 8 when overclocking High BCLK or High CPU frequency.
Conguration options: [Auto] [Level 0] - [Level 10]
Eventual CPU Standby Voltage
The congurations for this option differs when LN2 Mode is enabled or disabled.
LN2 Disabled: [Auto] [0.800] - [1.800]
LN2 Enabled: [Auto] [0.800] - [2.100]
Eventual PLL Termination Voltage
Conguration options: [Auto] [0.350] - [2.400]
Eventual DMI Voltage
Conguration options: [Auto] [0.300] - [2.100]