User Manual

32
Pro WS W680-ACE Series BIOS Manual
GT CEP Enable
Allows you to enable or disable GT CEP (Current Excursion Protection) Support. Uses
pCode Mailbox Command 0x37, Sub-command 0x1. Set Databit3 to 1.
Configuration options: [Auto] [Disabled] [Enabled]
SA CEP Enable
Allows you to enable or disable SA CEP (Current Excursion Protection) Support. Uses
pCode Mailbox Command 0x37, Sub-command 0x1. Set Databit3 to 1.
Configuration options: [Auto] [Disabled] [Enabled]
IA SoC Iccmax Reactive Protector
Configuration options: [Auto] [Disabled] [Enabled]
Inverse Temperature Dependency Throttle
Configuration options: [Auto] [Disabled] [Enabled]
IA VR Voltage Limit
Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage
allowed at any given time. Range is 0 - 7999mV. Uses BIOS VR mailbox command
0x8.
Configuration options: [Auto] [0] - [7999]
CPU DLVR Bypass Mode Enable
Configuration options: [Auto] [Disabled] [Enabled]
CPU SVID Support
Disable this item to stop the CPU from communicating with the external voltage
regulator.
Configuration options: [Auto] [Disabled] [Enabled]
Tweaker’s Paradise
Realtime Memory Timing
Allows you to enable or disable realtime memory timing. When set to [Enabled], the
system will allow performing realtime memory timing changes after MRC_DONE.
Configuration options: [Disabled] [Enabled]
SPD Write Disable
Allows you to enable or disable setting SPD Write Disable. For security
recommendations, SPD write disable bit must be set.
Configuration options: [TRUE] [FALSE]
PVD Ratio Threshold
For the Core Domain PLL, the threshold to switch to lower post divider is 15 by
default. You can set a value lower than 15 when pushing high BCLK so that Digitally
Controlled Oscillator (DCO) remains at reasonable frequency.
Configuration options: [Auto] [1] - [40]
SA PLL Frequency Override
Allows you to configure Sa PLL Frequency.
Configuration options: [Auto] [3200 MHz] [1600 MHz]