User Manual
Table Of Contents
- 1. Knowing BIOS
- 2. BIOS setup program
- 3. Managing and updating your BIOS
- 4. BIOS menu screen
- 5. Main menu
- 6. Ai Tweaker menu
- 7. Advanced menu
- 7.1 Trusted Computing
- 7.2 AMD fTPM configuration
- 7.3 Redfish Host Interface Settings
- 7.4 UEFI Variables Protection
- 7.5 Serial Port Console Redirection
- 7.6 CPU Configuration
- 7.7 PCI Subsystem Settings
- 7.8 USB Configuration
- 7.9 Network Stack Configuration
- 7.10 NVMe Configuration
- 7.11 HDD/SSD SMART Information
- 7.12 SATA Configuration
- 7.13 APM Configuration
- 7.14 Onboard Devices Configuration
- 7.15 PCIe Redriver Tuning
- 7.16 AMD Mem Configuration Status
- 7.17 AMD PBS
- 7.18 AMD Overclocking
- 7.19 AMD CBS
- 7.20 Third-party UEFI driver configurations
- 8. Monitor menu
- 9. Boot menu
- 10. Tool menu
- 11. Server Mgmt menu
- 12. Exit menu
Pro WS sTR5 Series BIOS Manual
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The following item appears only when TwrwrSd Ctrl is set to [Manual].
TwrwrSd
Specifies the Write to Write turnaround timing in the same DIMM.
Valid values: 0x1 - 0xF.
TwrwrDd Ctrl
[Auto] Follow default setting.
[Manual] Manually specify.
The following item appears only when TwrwrDd Ctrl is set to [Manual].
TwrwrDd
Specifies the Write to Write turnaround timing in a different DIMM.
Valid values: 0x1 - 0xF.
Twrrd Ctrl
[Auto] Follow default setting.
[Manual] Manually specify.
The following item appears only when Twrrd Ctrl is set to [Manual].
Twrrd
Specifies the Write to Read turnaround timing. Valid values: 0x1 -
0xF.
Trdwr Ctrl
[Auto] Follow default setting.
[Manual] Manually specify.
The following item appears only when Trdwr Ctrl is set to [Manual].
Trdwr
Specifies the Read to Write turnaround timing. Valid values: 0x1 -
0x1F. The value is in hex.
DFI Channel Timing Configuration
RxDatChnDly
Configures the RX timing between memory controller and PHY.
Higher value may enable increased memory frequency at the expense
of increased latency.
Configuration options: [Auto] [1] [2]
TxDatChnDly
Configures the TX timing between memory controller and PHY.
Higher value may enable increased memory frequency at the expense
of increased latency.
Configuration options: [0] [1] [2] [3] [Auto]
TxCtrlChnDly
Configures the command timing between memory controller and PHY.
Higher value may enable increased memory frequency at the expense
of increased latency.
Configuration options: [0] [1] [Auto]