User Manual
Table Of Contents
- 1. Knowing BIOS
- 2. BIOS setup program
- 3. Managing and updating your BIOS
- 4. BIOS menu screen
- 5. Main menu
- 6. Ai Tweaker menu
- 7. Advanced menu
- 7.1 Trusted Computing
- 7.2 AMD fTPM configuration
- 7.3 Redfish Host Interface Settings
- 7.4 UEFI Variables Protection
- 7.5 Serial Port Console Redirection
- 7.6 CPU Configuration
- 7.7 PCI Subsystem Settings
- 7.8 USB Configuration
- 7.9 Network Stack Configuration
- 7.10 NVMe Configuration
- 7.11 HDD/SSD SMART Information
- 7.12 SATA Configuration
- 7.13 APM Configuration
- 7.14 Onboard Devices Configuration
- 7.15 PCIe Redriver Tuning
- 7.16 AMD Mem Configuration Status
- 7.17 AMD PBS
- 7.18 AMD Overclocking
- 7.19 AMD CBS
- 7.20 Third-party UEFI driver configurations
- 8. Monitor menu
- 9. Boot menu
- 10. Tool menu
- 11. Server Mgmt menu
- 12. Exit menu
Pro WS sTR5 Series BIOS Manual
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The following items appear only when Target Static Lane Control is set to [Enabled].
Target Static Lane Select Upper 32 bits
Static Lane Select for Upper 32 bits. The bit mask represents the bits
to be read.
Configuration options: [0] - [99999999]
Target Static Lane Select Lower 32 bits
Static Lane Select for Lower 32 bits. The bit mask represents the bits
to be read.
Configuration options: [0] - [99999999]
Target Static Lane Select ECC
Static Lane Select for ECC Lanes. The bit mask represents the bits to
be read.
Configuration options: [0] - [9]
Target Static Lane Value
Configuration options: [0] - [9]
Worst Case Margin Granularity
Configuration options: [Per Chip Select] [Per Nibble]
Read Voltage Sweep Step Size
This option determines the step size for Read Data Eye voltage
sweep.
Configuration options: [1] [2] [4]
Read Timing Sweep Step Size
This option supports step size for Read Data Eye.
Configuration options: [1] [2] [4]
Write Voltage Sweep Step Size
This option determines the step size for write Data Eye voltage
sweep.
Configuration options: [1] [2] [4]
Write Timing Sweep Step Size
This option supports step size for write Data Eye.
Configuration options: [1] [2] [4]
Memory Healing BIST
Allows you to enable a full memory test. The testing will increase the boot time.
BIOS mem BIST tests the full memory after training. Failing memory will be
repaired using soft or hard PPR depending on the PPC configuration. The test
will take 3 minutes per 16GN of installed memory. Self-Healing BIST runs the
JEDEC DRAM self healing if the device supports the feature. The DRAM will
do a hard repair for failing memory. The test will take 10 seconds per memory
rank per channel.
Configuration options: [Disabled] [BIOS Mem BIST] [Self-Healing Mem BIST]
[BIOS and Self-Healing Mem BIST]
The following items appear only when Memory Healing BIST is set to [BIOS Mem BIST].
Mem BIST Test Select
Select the vendor specific tests to use with BIOS memory healing BIST.
Configuration options: [Vendor Tests Enabled] [Vendor Tests Disabled] [All
Tests - All Vendors]
Mem BIST Post Package Repair Type
For DRAM errors found in the BIOS memory BIST select the repair type, soft,
hard, or test only and do not attempt to repair.
Configuration options: [Soft Repair] [Hard Repair] [No Repairs - Test only]