User Manual
Table Of Contents
- 1. Knowing BIOS
- 2. BIOS setup program
- 3. Managing and updating your BIOS
- 4. BIOS menu screen
- 5. Main menu
- 6. Ai Tweaker menu
- 7. Advanced menu
- 7.1 Trusted Computing
- 7.2 AMD fTPM configuration
- 7.3 Redfish Host Interface Settings
- 7.4 UEFI Variables Protection
- 7.5 Serial Port Console Redirection
- 7.6 CPU Configuration
- 7.7 PCI Subsystem Settings
- 7.8 USB Configuration
- 7.9 Network Stack Configuration
- 7.10 NVMe Configuration
- 7.11 HDD/SSD SMART Information
- 7.12 SATA Configuration
- 7.13 APM Configuration
- 7.14 Onboard Devices Configuration
- 7.15 PCIe Redriver Tuning
- 7.16 AMD Mem Configuration Status
- 7.17 AMD PBS
- 7.18 AMD Overclocking
- 7.19 AMD CBS
- 7.20 Third-party UEFI driver configurations
- 8. Monitor menu
- 9. Boot menu
- 10. Tool menu
- 11. Server Mgmt menu
- 12. Exit menu
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Pro WS sTR5 Series BIOS Manual
The following items appear only when Discrete USB4 Support is set to [Enabled].
PCIe Bus Number
Reserve Discrete USB4 PCIe Bus number per port (16 ~ 56).
Configuration options: [16] - [56]
PCIe Non-Prefetchable MMIO
Reserve Discrete USB4 PCIe Non-Prefetchable MMIO per port (256 ~ 4096 MB).
Configuration options: [256] - [4096]
PCIe Prefetchable MMIO
Reserve Discrete USB4 PCIe Prefetchable MMIO per port (256 ~ 16384 MB).
Configuration options: [256] - [16384]
ACPI D3 Support
Allows you to enable or disable Discrete USB4 ACPI D3 Support.
Configuration options: [Disabled] [D3Hot] [D3Cold]
XHCI Port0~1 Speed
Allows you to configure the Discrete USB4 XHCI Port0~1 Speed.
Configuration options: [Gen1x1] [Gen1x2] [Gen2x1] [Gen2x2]
Unused GPP Clocks Off
Allows you to enable or disable Unused GPP Clocks.
Configuration options: [Disabled] [Enabled]
Onboard LAN RTL8125BS
Allows you to enable or disable Onboard LAN RTL8125BS.
Configuration options: [Disabled] [Enabled]
WLAN Power Control
Allows you to enable or disable WLAN Power Control.
Configuration options: [Disabled] [Enabled]
MITT/WITT Selection
Configuration options: [MITT Only] [WITT Only] [Both disable]
External CLK Control
[Auto] 100Mhz CGPLL generated by default.
[eCLK0, GPP0-PCIe, GPP0-CPU] External input thru GPP1.
• Switch APU clocks source mapping will get stuck immediately (post code:
B0005A5A), manual press cold reset button to bypass.
• The following items appear only when External CLK Control is set to [eCLK0,
GPP0-PCIe, GPP0-CPU].
GPP0 SCC control
Allows you to enable or disable Spread-Spectrum on GPP0 (RC26012A OUT0) and PCIe
Slots (RC26012A OUT0, 0).
Configuration options: [Enabled] [Disabled]