User Manual

ASUS P9A-I Series
4-21
AtomicOp Egress Blocking [Disabled]
If your PCIe device supports this function and this item is set to [Enabled], outbound
AtomicOp Requests via Egress ports will be blocked. Conguration Options: [Disabled]
[Enabled]
IDO Request Enable [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to allow setting the
number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated. Conguration
Options: [Disabled] [Enabled]
IDO Completion Enable [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to allow setting the
number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated. Conguration
Options: [Disabled] [Enabled]
LTR Mechanism Enable [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to enable the Latency
Tolerance Reporting (LTP) Mechanism. Conguration Options: [Disabled] [Enabled]
End-End TLP Prefix Blocking [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to block forwarding of
TLPs containing End-End TLP Prexes. Conguration Options: [Disabled] [Enabled]
Target Link Speed [Auto]
If your PCIe device supports this function, set this item to [Force to 2.5 GT/s] for downstream
ports. This sets an upper limit on link operational speed by restricting the values advertised
by the upstream component in its training sequences. When [Auto] is selected, hareware
initialized data will be used. Conguration Options: [Auto] [Force to 2.5 GT/s] [Force to 5.0
GT/s]
Clock Power Management [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to permit the device
to use CLKREQ# signal for power management of link clock in accordance to the protocol
dened in appropriate form factor specication. Conguration Options: [Disabled] [Enabled]
Compliance SOS [Disabled]
If your PCIe device supports this function, set this item to [Enabled] to force LTSSM to send
SKP Ordered Sets between sequences when sending Compliance Pattern or Modied
Compliance Pattern. Conguration Options: [Disabled] [Enabled]
Hardware Autonomous Width [Enabled]
If your PCIe device supports this function, set this item to [Disabled] to disable the hardware's
ability to change link width except width size reduction for the purpose of correcting unstable
link operation. Conguration Options: [Disabled] [Enabled]
Hardware Autonomous Speed [Enabled]
If your PCIe device supports this function, set this item to [Disabled] to disable the hardware's
ability to change link speed except speed rate reduction for the purpose of correcting unstable
link operation. Conguration Options: [Disabled] [Enabled]