Specifications

2-16
Chapter 2: BIOS information
Secondary Timings
DRAM RAS# to RAS# Delay [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
DRAM REF Cycle Time [Auto]
Congurationoptions:[Auto][1DRAMClock]–[511DRAMClock]
DRAM Refresh Interval [Auto]
Congurationoptions:[Auto][1DRAMClock]–[65535DRAMClock]
DRAM WRITE Recovery Time [Auto]
Congurationoptions:[Auto][1DRAMClock]–[16DRAMClock]
DRAM READ to PRE Time [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
DRAM FOUR ACT WIN Time [Auto]
Congurationoptions:[Auto][1DRAMClock]–[255DRAMClock]
DRAM WRITE to READ Delay [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
DRAM CKE Minimum pulse width [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
DRAM CAS# Write Latency [Auto]
Congurationoptions:[Auto][1DRAMClock]–[31DRAMClock]
RTL IOL control
DRAM RTL Initial Value [Auto]
Congurationoptions:[Auto][1DRAMClock]–[63DRAMClock]
DRAM RTL (CHA) [Auto]
Congurationoptions:[Auto][1DRAMClock]–[63DRAMClock]
DRAM RTL (CHB) [Auto]
Congurationoptions:[Auto][1DRAMClock]–[63DRAMClock]
DRAM IO-L (CHA) [Auto]
Configuration options: [Auto] [Delay 1 Clock] - [Delay 15 Clock]
DRAM IO-L (CHB) [Auto]
Configuration options: [Auto] [Delay 1 Clock] - [Delay 15 Clock]
Third Timings
tRDRD [Auto]
Congurationoptions:[Auto][1DRAMClock]–[7DRAMClock]
tRDRD_dr [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
tRDRD_dd [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]
tWRRD [Auto]
Congurationoptions:[Auto][1DRAMClock]–[63DRAMClock]
tWRRD_dr [Auto]
Congurationoptions:[Auto][1DRAMClock]–[15DRAMClock]