User's Manual

Intel
®
820 Chipset Design Guide ix
Revision History
Revision Description Date
-001 Initial Release. November 1999
-002
• Added dual-processor schematics (Appendix B).
• Uni-processor schematics have been updated (Appendix A). See the
schematic revision history page at the end of Appendix A for details.
- The following update is not in the schematic revision history.
Cap C249 (schematic page 9) has been changed from 0.022 uF to
0.047 uF.
December 1999
-003
• Updated the text descriptions in the two paragraphs in Section 4.2.3,
“MCH to DRCG”.
• Updated the first paragraph in Section 2.6.2.5, “RSL Signal Layer
Alternation“.
January 2000
-004 • Minor edits for clarity July 2000