User's Manual

Intel

820 Chipset Design Guide 2-57

Layout/Routing Guidelines

2.13.2 Ultra ATA/66 Cable Detection

The Intel

820 chipset can use two methods to detect the cable type. Each mode requires a

different motherboard layout.

Host-Side Detection (BIOS Detects Cable Type Using GPIOs)

Host side detection requires the use of two GPI pins (1 per IDE controller). The proper way to

connect the PDIAG/CBLID signal of the IDE connector to the host is shown in Figure 2-46. All

IDE devices have a 10 KΩ pull-up resistor to 5 volts. The GPI and GPIO pins on the ICH and GPI

pins on the FWH Flash BIOS are not 5 volt tolerant. This requires a resistor divider so that 5 volts

will not be driven to the ICH or FWH Flash BIOS pins. The proper value of the series resistor is

15 KΩ (as shown in Figure 2-46). This creates a 10 KΩ / 15 KΩ resistor divider and produces

approximately 3 volts for a logic high.

This mechanism allows the host, after diagnostics, to sample PDIAG/CBLID. If PDIAG/CBLIB is

high then there is 40-conductor cable in the system and ATA modes 3 and 4 should not be enabled.

If PDIAG/CBLID is low then there is an 80-conductor cable in the system.

Figure 2-46. Host-Side IDE Cable Detection

80-Conductor

IDE Cable

IDE Drive

10 K

Ω

PDIAG

ICH

GPIO

To Secondary

IDE Connector

Open

15 K

Ω

40-Conductor

Cable