User's Manual

Layout/Routing Guidelines
2-54 Intel
®
820 Chipset Design Guide
The recommendation for the layout and the schematic example are shown below. Layout
guidelines are:
•
Place the transistor and stub as close as possible to MCH (or place the transistor pad on top of
trace)
•
The max stub for transistor is less than 0.25”
•
The recommended loading of transistor is less than 5 pf.
•
For dual processor design, the stub is recommended to place on the stub of the MCH and as
close as possible to the MCH, and is less than 0.25”
Note: This circuit is only recommended for the debug situation that requires to set the IOQ depth equal to
1. For the production, do not add this circuit, since the overall system performance will be
degraded. Also, Intel does not guarantee the above layout recommendation will work under the
worst case condition.
In-Target Probe (ITP)
It is important that all of the processor electrical characteristic requirements are met. It is
recommended that prototype boards implement the ITP connector.
Logic Analyzer Interface (LAI)
Note that 1 KΩ resistors that are used to pull-up several processor signals in the schematics in
Appendix A, “Reference Design Schematics: Uni-Processor” and Appendix B, “Reference Design
Schematics: Dual-Processor” (e.g., HINIT#, IGNNE#, SMI#, etc.) preclude use of the Intel
Pentium III processor LAI. The Intel Pentium III processor LAI will function correctly with these
1KΩ pull-up resistors.
Figure 2-45. HA7# Strapping Option Example Circuit (For Debug Purposes Only)
CPURST#
CPUCLK
R2
2.7 K
Ω
ΩΩ
Ω
5V
5V5V
2
5
6
4
1
3
1
2
3
4
5
6
QQ
/Q /Q
D
/PRE
/CLR
/PRE
/CLR
D
CLK
CLK
74F74 74F74
2N3904
2N3904
HA7
R2
4.7 K
Ω
ΩΩ
Ω
R2
4.7 K
Ω
ΩΩ
Ω
jumper
4.7 K
Ω
ΩΩ
Ω