User's Manual

viii Intel
®
820 Chipset Design Guide
Tables
1-1 Intel
®
820 Chipset Platform Bandwidth Summary ........................................1-4
2-1 AGP 2X Data/Strobe Association .................................................................2-6
2-2 Placement Guidelines for Motherboard Routing Lengths .............................2-9
2-3 Copper Tab Area Calculation .....................................................................2-15
2-4 RSL Routing Layer Requirements ..............................................................2-21
2-5 Line Matching and Via Compensation Example.........................................2-24
2-6 Signal List ...................................................................................................2-28
2-7 AGP 2.0 Data/Strobe Associations.............................................................2-33
2-8 AGP 2.0 Routing Summary ........................................................................2-35
2-9 TYPDET#/VDDQ Relationship ...................................................................2-38
2-10 Connector/Add-in Card Interoperability ......................................................2-42
2-11 Voltage/Data Rate Interoperability..............................................................2-42
2-12 Segment Descriptions and Lengths for Figure 2-36 ...................................2-46
2-13 Processor and 82820 MCH Connection Checklist......................................2-49
2-14 Bus Request Connection Scheme for DP Intel
®
820 Chipset Designs.......2-52
2-15 ICH Codec Options.....................................................................................2-61
2-16 AC'97 SDIN Pulldown Resistors.................................................................2-63
3-1 AGTL+ Parameters for Example Calculations..............................................3-6
3-2 Example T
FLT_MAX
Calculations for 133 MHz Bus .......................................3-7
3-3 Example T
FLT_MIN
Calculations (Frequency Independent)...........................3-8
3-4 Trace Width Space Guidelines ...................................................................3-11
3-5 Host Clock Routing .....................................................................................3-12
4-1 Intel
®
820 Chipset Platform System Clocks..................................................4-1
4-2 Intel
®
820 Chipset Platform Clock Skews.....................................................4-3
4-3 Intel
®
820 Chipset Platform System Clock Cross-Reference .......................4-5
4-4 Placement Guidelines for Motherboard Routing Lengths .............................4-8
4-5 External DRCG Component Values ...........................................................4-10
4-6 Unused Output Termination........................................................................4-12
4-7 DRCG Ratio................................................................................................4-12
5-1 28Ω Stackup Examples ................................................................................5-3
5-2 3D Field Solver vs ZCALC............................................................................5-4
6-1 Intel
®
820 Chipset Component Thermal Design Power................................6-7
6-2 Glue Chip 3 Vendors ....................................................................................6-8