User's Manual

Intel
®
820 Chipset Design Guide 2-51
Layout/Routing Guidelines
NOTES:
1. For single processor designs, the AGTL+ bus can be dual-ended or single-ended termination based on
simulation results. Single-ended termination is provided by the processor.
2. This checklist supports Intel
®
Pentium
®
II processors at all current speeds, Intel
®
Pentium
®
III processors to
a FMB guideline of 19.3A, and future Intel
®
Pentium
®
III processors to the current FMB guideline of 18.4A.
Clock Signals
BCLK
Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics). To reduce pin-to-pin
skew, tie host clock outputs together at the
clock driver then route to the MCH and
processor.
Use separate BCLK from TAP and CPU0,
or use ganged clock. Terminate as
described.
PICCLK
Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics)
Use separate PICCLK from CPU0.
Terminate as described.
Other Signals
BSEL0
100/133 MHz support: 220 Ω pull up to 3.3V,
connected to PWRGOOD logic such that a
logic low on BSEL0 negates PWRGOOD
Connect to 2
nd
processor
BSEL1
220 Ω pull up to 3.3V, connect to CK133
SEL133/100# pin. Connect to MCH HL10 pin
via 8.2 KΩ series resistor.
Connect to 2
nd
processor
EMI[5:1]
Tie to GND. Zero ohm resistors are an option
instead of direct connection to GND.
Implement in same manner as CPU0.
SLOTOCC#
Tie to GND, leave it N/C, or could be
connected to powergood logic to gate system
from powering on if no processor is present.
If used, 1 KΩ – 10 KΩ pull up to any voltage.
Implement in same manner as CPU0.
TESTHI
1K–100KΩ pull up to Vcc2.5
If a legacy design pulls this up to VCC
CORE
,
use a 1 KΩ – 10 KΩ pull up
Implement in same manner as CPU0.
VID[4:0]
Connect to on-board VR or VRM. For on-
board VR, 10 KΩ pull up to power-solution
compatible voltage required (usually pulled
up to input voltage of the VR). Some of these
solutions have internal pull-ups. Optional
override (jumpers, ASIC, etc.) could be used.
May also connect to system monitoring
device.
Implement in same manner as CPU0.
CPU0 and CPU1 should have different
VR/VRMs.
Power
VCC
CORE
Connect to core voltage regulator. Provide
high & low frequency decoupling.
Implement in same manner as CPU0.
V
TT
Connect to 1.5V regulator. Provide high and
low frequency decoupling.
Implement in same manner as CPU0.
No Connects
Reserved
The following pins must be left as no-
connects: A16, A47, A88, A113, A116, B12,
B20, B76, and B112.
Implement in same manner as CPU0.
Table 2-13. Processor and 82820 MCH Connection Checklist
1,2
(Continued)
CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1)