User's Manual

Intel
®
820 Chipset Design Guide vii
2-44 BREQ0# Circuitry for DP Systems..............................................................2-53
2-45 HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54
2-46 Host-Side IDE Cable Detection...................................................................2-57
2-47 Drive-Side IDE Cable Detection..................................................................2-58
2-48 Layout for Host- or Drive-Side IDE Cable Detection...................................2-59
2-49 Ultra ATA/66 Cable.....................................................................................2-59
2-50 Resistor Requirements for Primary IDE Connector ....................................2-60
2-51 Resistor Requirements for Secondary IDE Connector ...............................2-61
2-52 Tee Topology AC'97 Trace Length Requirements......................................2-62
2-53 Daisy-Chain Topology AC'97 Trace Length Requirements ........................2-62
2-54 USB Data Signals .......................................................................................2-65
2-55 PCI Bus Layout Example............................................................................2-67
2-56 External Circuitry for the ICH RTC..............................................................2-68
2-57 Diode Circuit Connecting RTC External Battery .........................................2-69
2-58 RTCRST External Circuit for the ICH RTC .................................................2-70
3-1 PICD[1,0] Uni-Processor Topology.............................................................3-12
3-2 PICD[1,0] Dual-Processor Topology...........................................................3-12
3-3 Test Load vs. Actual System Load .............................................................3-14
3-4 Aggressor and Victim Networks..................................................................3-17
3-5 Transmission Line Geometry: (A) Microstrip (B) Stripline...........................3-17
3-6 One Signal Layer and One Reference Plane..............................................3-21
3-7 Layer Switch with One Reference Plane ....................................................3-21
3-8 Layer Switch with Multiple Reference Planes (same type).........................3-21
3-9 Layer Switch with Multiple Reference Planes.............................................3-22
3-10 One Layer with Multiple Reference Planes.................................................3-22
3-11 Overdrive Region and V
REF
Guardband.....................................................3-25
3-12 Rising Edge Flight Time Measurement.......................................................3-25
4-1 Intel
®
820 Chipset Platform Clock Distribution .............................................4-2
4-2 Intel
®
820 Chipset Clock Routing Guidelines ...............................................4-4
4-3 CK133 to DRCG Routing Diagram ...............................................................4-6
4-4 MCH to DRCG Routing Diagram ..................................................................4-7
4-5 Direct Rambus* Clock Routing Dimensions..................................................4-7
4-6 Differential Clock Routing Diagram (Section ‘A’, ‘C’, & ‘D’)...........................4-9
4-7 Non-Differential Clock Routing Diagram (Section ‘B’)...................................4-9
4-8 Termination for Direct Rambus* Clocking Signals CFM/CFM# ....................4-9
4-9 DRCG Impedance Matching Network.........................................................4-10
4-10 DRCG Layout Example...............................................................................4-11
4-11 DRCG+ Frequency Selection .....................................................................4-13
5-1 28Ω Trace Geometry ....................................................................................5-2
5-2 Microstrip and Stripline Cross-section for 28 Ω Trace ..................................5-4
5-3 7 mil Stackup (Not Routable)........................................................................5-5
5-4 4.5 mil Stackup .............................................................................................5-5
6-1 Intel
®
820 Chipset Power Delivery Example.................................................6-2
6-2 1.8V and 2.5V Power Sequencing (Schottky Diode) ....................................6-4
6-3 Use a GPO to Reduce DRCG Frequency.....................................................6-6
6-4 Power Plane Split Example...........................................................................6-7