User's Manual

Layout/Routing Guidelines
2-40 Intel
®
820 Chipset Design Guide
During 3.3V AGP 2.0 operation, V
REF
must be 0.4VDDQ. However, during 1.5V AGP 2.0
operation, Vref must be 0.5VDDQ. This requires a flexible voltage divider for V
REF
. Various
methods of accomplishing this exist, and one such example is shown in Figure 2-32.
The flexible V
REF
divider shown in Figure 2-32 uses a FET switch to switch between the locally
generated V
REF
(for 3.3V add-in cards) and the source generated V
REF
(for 1.5V add-in cards).
Usage of the source generated V
REF
at the receiver is optional and is a product implementation
issue which is beyond the scope of this document.
Figure 2-32. AGP 2.0 VREF Generation & Distribution
AGP
Device
1.5V AGP
Card
VDDQ
GND
R9
300
1%
R11
200
1%
0.1uF
C10
VDDQ
REF
GND
MCH
R6
1K
R2
1K
R5
82
R4
82
500pF
C8
REF
U6
mosfet
R7
1K
O
+12V
TYPEDET#
VrefCG
VrefGC
VDDQ
The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.
500pF
C9
Note: R7 is the same resistor seen in
AGP VDDQ Generation Example Circuit
Figure (R1)
Place C10 close to the MCH
AGP
Device
3.3V AGP
Card
VDDQ
GND
R9
300
1%
R11
200
1%
0.1uF
C10
VDDQ
REF
GND
MCH
R6
1K
R2
1K
R5
82
R4
82
500pF
C8
REF
U6
mosfet
O
+12V
TYPEDET#
VrefCG
VrefGC
VDDQ
The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.
500pF
C9
R7
1K
Note: R7 is the same resistor seen in AGP
VDDQ Generation Example Circuit Figure
(R1)
Place C10 close to the MCH