User's Manual

Layout/Routing Guidelines

2-26 Intel

820 Chipset Design Guide

2.6.4.1 SIO Routing

The SIO signal must be routed from RIMM to RIMM as shown in Figure 2-17. The SIO signal

requires a 2.2 KΩ – 10 KΩ terminating resistor on the SOUT pin of the last RIMM. SIO is routed

with a standard 5 mil wide 60 Ω trace. The motherboard routing lengths for the SIO signal are the

same as RSL signals (see Figure 2-17).

2.6.4.2 Suspend-to-RAM Shunt Transistor

When an Intel

820 chipset system enters or exits Suspend-to-RAM, power will be ramping to the

MCH (i.e., it will be powering-up or powering-down). When power is ramping, the state of the

MCH outputs is not guaranteed. Therefore, the MCH could drive the CMOS signals and issue

CMOS commands. One of the commands (the only one the RDRAMs would respond to) is the

powerdown exit command. To avoid the MCH inadvertently taking the RDRAMs out of power-

down due to the CMOS interface being driven during power ramp, the SCK (CMOS clock) signal

must be shunted to ground when the MCH is entering and exiting Suspend-to-RAM. This shunting

can be accomplished using the NPN transistor shown in circuit shown in Figure 2-28. The

transistor should have a Cobo of 4 pf or less (i.e., MMBT3904LT1).

In addition, to match the electrical characteristics on the SCK signal, the CMD signal needs a

dummy transistor. This transistor’s base should be tied to ground (i.e., always turned off).

Figure 2-26. High-Speed CMOS Termination

MCH

RIMM_0 RIMM_1

Ω

Vterm

Ω

Figure 2-27. SIO Routing Example

0" - 3.50"

0.4" - 0.45"

SIN B36

A36 SOUT

2.2K

Ω

10K

Ω

82820

MCH