User's Manual

Intel
®
820 Chipset Design Guide 2-25
Layout/Routing Guidelines
2.6.3 Direct Rambus
*
Reference Voltage
The Direct Rambus* reference voltage (RAMREF) must be generated as shown in Figure 2-25.
RAMREF should be generated from a typical resistor divider using 2% tolerance resistors.
Additionally, RAMREF must be decoupled locally at EACH RIMM connector, at the resistor
divider and at the MCH. Finally, as shown in Figure 2-25, a 100 Ω series resistor is required near
the MCH. The RAMREF signal should be routed with a 10 mil wide trace.
2.6.4 High-speed CMOS Routing
•
The high-speed CMOS signals (CMD & SCK) must be routed using 28 Ω traces. Using the
recommended stackup, these signals will be 18 mils wide.
•
The high-speed CMOS signals must be length matched to the RSL signals within 1200 mils
(1.2in) due to a timing requirement between CMOS and RSL signals during NAP Exit and
PDN Exit.
•
The high-speed CMOS signals require termination as shown in Figure 2-26 due to the buffer
strengths in the MCH.
•
The resistors must be 91 Ω pullup and 39 Ω pulldown; they also must 2% or better for S3
mode reliability. The trace impedances remain 28 Ω.
Figure 2-25. RAMRef Generation Example Circuit
160
Ω
2%
R
I
M
M
Vterm
R3
C4
C10
C5
C8
0.1 uF 0 .1 uF
100 Ω
R1
R2
0.1 uF
0.1 uF
R
I
M
M
560
Ω
2%
RAMREFA
RAMREFB
MCH