User's Manual

Intel
®
820 Chipset Design Guide v
3.5 Definitions of Flight Time Measurements/Corrections and Signal Quality ..3-24
3.5.1 V
REF
Guardband............................................................................3-24
3.5.2 Ringback Levels.............................................................................3-24
3.5.3 Overdrive Region...........................................................................3-24
3.5.4 Flight Time Definition and Measurement .......................................3-25
3.6 Conclusion ..................................................................................................3-26
4 Clocking .....................................................................................................................4-1
4.1 Clock Generation ..........................................................................................4-1
4.2 Component Placement and Interconnection Layout Requirements..............4-6
4.2.1 14.318 MHz Crystal to CK133 .........................................................4-6
4.2.2 CK133 to DRCG ..............................................................................4-6
4.2.3 MCH to DRCG .................................................................................4-7
4.2.4 DRCG to RDRAM Channel..............................................................4-8
4.2.5 Trace Length....................................................................................4-8
4.3 DRCG Impedance Matching Circuit............................................................4-10
4.3.1 DRCG Layout Example..................................................................4-11
4.4 AGP Clock Routing Guidelines...................................................................4-11
4.5 Series Termination Resistors for CK133 Clock Outputs.............................4-11
4.6 Unused Outputs..........................................................................................4-12
4.7 Decoupling Recommendation for CK133 and DRCG .................................4-12
4.8 DRCG Frequency Selection and the DRCG+.............................................4-12
4.8.1 DRCG Frequency Selection Table and Jitter Specification ...........4-12
4.8.2 DRCG+ Frequency Selection Schematic.......................................4-13
5 System Manufacturing ...............................................................................................5-1
5.1 In Circuit LPC Flash BIOS Programming......................................................5-1
5.2 LPC Flash BIOS Vpp Design Guidelines......................................................5-1
5.3 Stackup Requirement ...................................................................................5-1
5.3.1 Overview ..........................................................................................5-1
5.3.2 PCB Materials..................................................................................5-2
5.3.3 Design Process................................................................................5-2
5.3.4 Test Coupon Design Guidelines ......................................................5-3
5.3.5 Recommended Stackup...................................................................5-3
5.3.6 Inner Layer Routing .........................................................................5-3
5.3.7 Impedance Calculation Tools...........................................................5-4
5.3.8 Testing Board Impedance................................................................5-4
5.3.9 Board Impedance/Stackup Summary ..............................................5-5
6 System Design Considerations..................................................................................6-1
6.1 Power Delivery..............................................................................................6-1
6.1.1 Terminology and Definitions ............................................................6-1
6.1.2 Intel
®
820 Chipset Customer Reference Board Power Delivery......6-2
6.1.3 64/72Mbit RDRAM Excessive Power Consumption ........................6-5
6.2 Power Plane Splits........................................................................................6-7
6.3 Thermal Design Power .................................................................................6-7
6.4 Glue Chip 3 (Intel
®
820 Chipset Glue Chip) .................................................6-8
A Reference Design Schematics: Uni-Processor......................................................... A-1
A.1 Reference Design Feature Set .................................................................... A-1
B Reference Design Schematics: Dual-Processor....................................................... B-1
B.1 Reference Design Feature Set .................................................................... B-1