User's Manual

Layout/Routing Guidelines
2-14 Intel
®
820 Chipset Design Guide
All 4 layers of the motherboard require correct grounding between the RSL signals on the
motherboard:
•
Layer 1 = Ground Isolation
•
Layer 2 = Ground Plane
•
Layer 3 = Ground Reference in the Power Plane
•
Layer 4 = Ground Isolation
All ground vias and pins MUST be connected to all 4 layers.
2.6.2.4 Direct Rambus* Connector Compensation
The RIMM connector inductance causes an impedance discontinuity on the Direct Rambus*
channel. This may reduce voltage and timing margin.
To compensate for the inductance of the connector, approximately 0.65 pF–0.85 pF compensating
capacitive tab (C-TAB) is required on each RSL connector pin. This compensating capacitance
must be added to the following connector pins at each connector:
LCTM LCTM#
RCTM RCTM#
LCFM LCFM#
RCFM RCFM#
LROW[2:0] RROW[2:0]
LCOL[4:0] RCOL[4:0]
RDQA[8:0] LDQA[8:0]
RDQB[8:0] LDQB[8:0]
SCK CMD
This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each
connector. The target value is approximately 0.65 pF–0.85 pF. The copper tab area for the
recommended stackup was determined through simulation. The placement of the copper tabs can
be on any signal layer, independent of the layer on which the RSL signal is routed.
Equation is an approximation that can be used for calculating copper tab area on an outer layer.
Equation 2-1. Approximate Copper Tab Area Calculation
Length*Width = Area = C
plate
* Thickness of prepreg / [(ε
0
) (ε
r
) (1.1)]
Where:
— ε
0
= 2.25 x 10
-16
Farads/mil
— ε
r
= Relative dielectric constant of prepreg material
— Thickness of prepreg = Stackup dependent
— Length, Width = Dimensions in mils of copper plate to be added
— Factor of 1.1 accounts for fringe capacitance.
Based on the stackup requirement in Section 5.3, “Stackup Requirement” on page 5-1 the copper
tab area should be 2800 to 3600 sq mils. Different stackups require different copper tab areas.
Table 2-3 shows example copper tab areas.