User's Manual

iv Intel
®
820 Chipset Design Guide
2.9 System Bus Design ....................................................................................2-46
2.9.1 100/133 MHz System Bus .............................................................2-46
2.9.2 System Bus Ground Plane Reference...........................................2-47
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM) .................................2-47
2.11 Processor CMOS Pullup Values.................................................................2-49
2.12 Additional Host Bus Guidelines ..................................................................2-52
2.13 Ultra ATA/66 ...............................................................................................2-56
2.13.1 Ultra ATA/66 Detection..................................................................2-56
2.13.2 Ultra ATA/66 Cable Detection........................................................2-57
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements ................................2-60
2.14 AC’97 ..........................................................................................................2-61
2.14.1 AC’97 Signal Quality Requirements...............................................2-63
2.14.2 AC’97 Motherboard Implementation..............................................2-63
2.15 USB ............................................................................................................2-65
2.16 ISA (82380AB)............................................................................................2-66
2.16.1 ICH GPIO connected to 82380AB .................................................2-66
2.16.2 Sub Class Code.............................................................................2-66
2.17 IOAPIC Design Recommendation ..............................................................2-66
2.18 SMBus/Alert Bus.........................................................................................2-67
2.19 PCI..............................................................................................................2-67
2.20 RTC ............................................................................................................2-67
2.20.1 RTC Crystal ...................................................................................2-68
2.20.2 External Capacitors .......................................................................2-68
2.20.3 RTC Layout Considerations...........................................................2-69
2.20.4 RTC External Battery Connection..................................................2-69
2.20.5 RTC External RTCRST Circuit.......................................................2-70
2.20.6 RTC Routing Guidelines ................................................................2-70
2.20.7 VBIAS DC Voltage and Noise Measurements...............................2-71
3 Advanced System Bus Design ..................................................................................3-1
3.1 Terminology and Definitions .........................................................................3-1
3.2 AGTL+ Design Guidelines ............................................................................3-4
3.2.1 Initial Timing Analysis ......................................................................3-5
3.2.2 Determine General Topology, Layout, and Routing Desired ...........3-8
3.2.3 Pre-Layout Simulation .....................................................................3-8
3.2.4 Place and Route Board..................................................................3-10
3.2.5 Post-Layout Simulation..................................................................3-13
3.2.6 Validation .......................................................................................3-14
3.3 Theory.........................................................................................................3-15
3.3.1 AGTL+ ...........................................................................................3-15
3.3.2 Timing Requirements.....................................................................3-16
3.3.3 Cross-talk Theory ..........................................................................3-16
3.4 More Details and Insight.............................................................................3-19
3.4.1 Textbook Timing Equations ...........................................................3-19
3.4.2 Effective Impedance and Tolerance/Variation ...............................3-20
3.4.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling...................................................................3-20
3.4.4 Clock Routing ................................................................................3-23