User's Manual

Layout/Routing Guidelines
2-8 Intel
®
820 Chipset Design Guide
2.6.1 Stackup
The perfect matching of transmission line impedance and uniform trace length are essential for the
Direct RDRAM interface to work properly. Maintaining 28 Ω (±10%) loaded impedance for every
RSL (Direct Rambus* Signaling Level) signal has changed the requirements for trace width and
prepreg thickness for the Intel
®
820 chipset platform (refer to Section 5.3, “Stackup Requirement”
on page 5-1).
Achieving a 28 Ω nominal impedance with a traditional 7 mil prepreg requires 28 mil wide traces.
These traces are too wide to break out of the two rows of RSL balls on the MCH. To reduce trace
width, a 4.5 mil thick prepreg is required. This thinner prepreg allows 18 mil wide traces to meet
the 28 Ω (±10%) nominal impedance requirement. Refer to Section 5.3, “Stackup Requirement” on
page 5-1 for detailed stackup requirements.
2.6.2 Direct Rambus
*
Layout Guidelines
The signals on the Direct Rambus
*
Channel are broken into three groups: RSL signals, CMOS
signals, and Clocking signals. The signal groups are:
•
RSL Signals
— DQA[8:0]
—DQB[8:0]
—RQ[7:0]
•
CMOS Signals
— CMD (high-speed CMOS signal)
— SCK (high-speed CMOS signal)
—SIO
•
Clocking Signals
—CTM, CTM#
—CFM, CFM#
2.6.2.1 RSL Routing
The RSL signals enter the first RIMM on the left side, propagate through the RIMM, and exit on
the right. The signal continues through the rest of the existing RIMMs until it is terminated at
V
term
. All unpopulated slots must have continuity modules in place to ensure that the signals
propagate to the termination.