User's Manual

11-29-1999_14:44
BULK DECOUPLING
37
22UF
C367
21
10UF
C64 C65
10UF
C89
10UF
C106
10UF
10UF
C108 C114
10UF
10UF
C115
10UF
C125 C127
10UF
10UF
C128
0.01UF
C129
0.01UF
C130 C131
0.01UF
0.01UF
C132
0.1UF
C133
0.1UF
C134 C135
0.1UF
C136
0.1UF
22UF
C369
12
C370
22UF
21
22UF
C371
12
0.1UF
C137 C138
0.1UF
C139
0.1UF
C141
0.1UF
0.1UF
C145 C146
0.1UF
C147
0.1UF
0.1UF
C148
0.1UF
C149
0.1UF
C150 C151
0.1UF
0.1UF
C152 C153
0.1UF
0.1UF
C154 C163
0.1UF
0.1UF
C172 C175
0.1UF
0.1UF
C176
0.1UF
C177
0.1UF
C178 C181
0.1UF
0.1UF
C188 C195
0.1UF
0.1UF
C216 C238
0.1UF
0.1UF
C240 C259
0.1UF
0.1UF
C310
C330
0.1UF
C331
0.1UF
0.1UF
C332 C333
0.1UF
0.1UF
C334 C337
0.1UF
0.1UF
C338 C339
0.1UF
0.1UF
C340
0.1UF
C341
10UF
C342C343
10UF
10UF
C344
10UF
C345
C346
10UF
10UF
C351C357
10UF
C363
10UF
C364
10UF 10UF
C365
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
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B
C
D
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D
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TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
+
VCC3_3
++
+
VCC3_3VCC3_3
VCC5
VCC12-VCC12
VCCVID VCCVID
VTT1_5
VCC2_5
VCC3_3SBY
VCCVID1 VCCVID1
VCC2_5 DecouplingVCC3_3 DecouplingVCC3_3 Decoupling Termination Decoupling
Core Voltage Decoupling
Bulk Power Decoupling
Bulk Decoupling
Place caps at VTT pins on Slot 1 connector.