User's Manual

11-29-1999_14:46
SERIAL PORTS
27
CTS1_C
DTR1_C
DCD1_C
RTS0_C
DTR0_C
RXD0_C
DSR0_C
TXD1_C
RXD1_C
RTS1_C
U6
19
18
17
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
16
20
TXD1
14
14
DCD#1
14
RTS#1
14
RXD1
14
CTS#1
14
RI#1
14
DSR#1
14
DTR#1
DCD0_C
CTS0_C
TXD0_C
14
DTR#0
14
DSR#0
14
RI#0
14
CTS#0
14
RXD0
14
RTS#0
14
DCD#0
TXD0
14
U4
20
16
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
17
18
19
RI0_C
11 ICH_RI#
J6
A5
A9
A4
A8
A3
A7
A2
A6
A1
J7
4
9
87
65
3
2
10
1
DSR1_C
R69 47K
RI_Q
47K R70
10K R369
RI_CR
CR2
1
2
3
1UF
C92
CP1
100PF
36
100PF
CP8
45
CP8
100PF
72
CP8
100PF
36
100PF
CP1
45
100PF
CP8
18
100PF
CP1
81
CP1
100PF
72
100PF
CP7
81
100PF
CP6
45
CP7
100PF
54
100PF
CP7
36
CP6
100PF
81
100PF
CP6
27
100PF
CP6
63
Q1
1
3
2
100PF
CP7
72
RI1_C
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC12-
VCC5 VCC12
RY0
RY1
RY2
DA1
RY3
DA2
RY4
GND
VCC12
RA0
RA1
RA2
DY0
DY1
RA3
DY2
RA4
VCC-12
DA0
VCC
GD75232
RY0
RY1
RY2
DA1
RY3
DA2
RY4
GND
VCC12
RA0
RA1
RA2
DY0
DY1
RA3
DY2
RA4
VCC-12
DA0
VCC
GD75232
VCC12VCC5
VCC12-
DB25_DB9_STK
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
GND
VCC3_3SBY
BAT54C
2N7002LT1
1
3
2
COM2 is a 2x5 pin header for a cabled port.
COM1
COM2
Serial Ports