User's Manual

11-29-1999_14:46
SYSTEM
20
GPIO23_FPLED11
U14
14
7
56
U14
43
7
14
R253
330
IRRX
14
1M
R252
SP1
1
2
24
IDEACTS#
24
IDEACTP#
R345
10K
R344
10K
R352
68
R353
68
JP24
1
2
3
JP23
3
2
1
R326
4.7K
JP22
3
2
1
4.7K
R316
14
PWM1
R329
4.7K
R350
2.2K
11
SPKR
P_BEEP
JP25
3
2
1
15
AC97_SPKR
IDE_ACTIVE
11
PWRBTN#
TACH2
R257
0K
5%
82
R357
14
IRTX
J25
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
470
R356
R358
4.7K
5%
KEYLOCK#
14
R355
220
R289
330
CR7
2
1
IRTX_R
HDLED_R
PLED_R
PWRBTN_FP#
SPKR_FP
SPKR_Q
SPKR_ONBOARD
SBY_LED_CR
PC_BEEP
U19
89
7
14
U19
14
7
12
DUAL_COLOR
CR6
12
LED_PU0 LED_PU1
11GPIO26_FPLED
330
R246
4.7K
R234
C267
1UF
470PF
C354
470PF
C355
R359
100K
0.1UF
C327
C316
0.1UF
10K
R354
C322
0.1UF
C350
0.1UF 50V
2
1
C356
10UF 16V
1
2
0.1UF
C353
MMBT3904LT1
Q15
E
C
B
14
PWM2
SW1
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
SN74LVC07A
GND
VCC
VCC3_3SBYVCC3_3SBY
SN74LVC07A
GND
VCC
VCC3_3
VCC3_3SBY
VCC5
VCC3_3SBY
VCC3_3
VCC3_3
VCC3_3
VCC5
NEG
POS
+
VCC5
VCC5
VCC12
VCC12
VCC12
VCC3_3
FNT_PNL_CONN
VCC3_3
VCC5
VCC3_3
SN74LVC07A
GND
VCC
VCC3_3SBY
SN74LVC07A
GND
VCC
VCC3_3SBY
+ +
1
3
2
KEY
KEY
No stuff.
For test only
No stuff.
KEY
INFRARED
H.D. LED
PWM1
TACH2
PWM2
SPEAKER
POWER SW.
For test only
ICH has internal pullup and debounce on PWRBTN#
KEY
Speaker Circuit
KEY
KEY
KEYLOCK
POWER LED
Onboard LED indicates the standby well is on
PWM outputs from SIO need power buffers for driving fan inputs.
to prevent hot swapping memory.
For debug only.
System
Onboard Spkr JP25
Enable* 2-3
Disable 1-2