User's Manual

1911-29-1999_14:46
18,19
LILED
18,19
ACTLED
330
R61
R366
330
LILED
18,19
ACTLED
18,19
SPEEDLED
18
LI_J
ACT_J
SPEED_J
JP1 JP4 JP3
R60
330 330
R73
330
R78
18
LAN_RSMRST#
11,33
RSMRST#
TDN
18
18
TDP
J18
3
2
1
RJ4_J
TXC_J
RJ_7_J
RXC_J
LI_CR
ACT_CR
49.9-1%
R26
49.9-1%
R20
75 R6 75 R365 75 R8 75 R10
49.9-1%
R62
49.9-1%
R364
18
RDP
18 RDN
XC_R
TD_C
RD_C
0.1UF
C61
0.1UF
C79
C31
0.1UF
470PF
C5
J2
15
16
13
14
1 2
6
5
4
3
8 11
7
9
12
10
18 17
RDC_J
TDC_J
0.1UF
C78
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
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D
C
B
A
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD
3.03
OF 38
R
VCC3_3 VCC3_3
RJMAG
SHLD1 SHLD2
TD+
TD-
RD+
RD-
TDC RDC
RJ-4
RJ-5
RJ-7
RJ-8
TXC RXC
RJ-45
LAN
LAN
For debug only. Hold LAN in reset.
Place termination resistors close to 82559.
No stuff JP1,JP3,JP4,R60,R73,R78.
No stuff C61, C79.
No stuff C31.
C5 must be rated at 1500V.
No stuff C5.
82559 LAN
J17
Enable* 1-2
Disable 2-3