User's Manual

11-18-1999_10:46 12
SUPER I/O
R313
4.7K
KBCLK
26
9
LPC_PME#
U17
27
18
45
44
15
11
10
93 65 53
96
85
14
83
9
67
77
30
95
84
98
87
92
90
16
17
78
75
74
73
72
71
70
69
6829
3
58
59
26
24
25
23
22
21
20
56
57
63
62
61
66
13
12
49
48
52
51
50
47
46
43
42
41
39
38
37
36
35
34
33
32
76 60 31
7
28
54
55
81
100
89
97
86
4
5
2
1
8
94
91
99
88
19
6
79
40
82
80
64
R312
4.7K
J20
2827
25 26
9
87
65
43
2423
2221
20
2
19
1817
1615
1413
1211
10
1
SIO_14MHZ
5
9,10,12
LAD3/FWH3
9,10,12
LAD1/FWH1
9,10,12
LAD0/FWH0
9,12
LDRQ#0
SIO_PCLK7
5,12
26
MDAT
MCLK
26
25
RXD0
25
TXD0
25
DSR#0
25
RTS#0
25
CTS#0
25
DTR#0
25
RI#0
25
DCD#0
25
RXD1
25
DSR#1
25
RTS#1
25
CTS#1
25
DTR#1
25
RI#1
25
DCD#1
26
MTR#0
26
DIR#
26
HDSEL#
26
INDEX#
26
TRK#0
24
SLIN#
26
RDATA#
24
PAR_INIT#
26
DSKCHG#
24
AFD#
24
STB#
24
SLCT
24
PE
24
BUSY
24
ACK#
24
ERR#
8,32
KBRST#
8,32
A20GATE
SERIRQ
8,12,21,32
18
PWM1
9
LPC_SMI#
27
MIDI_IN
27
MIDI_OUT
27
J1BUTTON1
27
J1BUTTON2
27
J2BUTTON1
27
J2BUTTON2
27
JOY1X
27
JOY1Y
27
JOY2X
27
JOY2Y
9,10,12
LAD2/FWH2
26
KBDAT
25
TXD1
18
TACH2
18
PWM2
26
DRVDEN#0
18
KEYLOCK#
26
DRVDEN#1
26
DS#0
26
STEP#
26
WDATA#
26
WGATE#
26
WRTPRT#
9,10,12 LAD3/FWH3
9,10,12 LAD2/FWH2
9,10,12 LAD1/FWH1
9,10,12 LAD0/FWH0
9,10,12 LFRAME#/FWH4
6,8,10,11,12,16,19,20,21,22 PCIRST#
5,12 SIO_PCLK7
9,12 LDRQ#0
8,12,21,32 SERIRQ
PDR7
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
24
PDR[7:0]
18
IRRX
18
IRTX
6,8,10,11,12,16,19,20,21,22
PCIRST#
5,9 MULT1_GPIO
LPCPD#
SYSOPT
9,10,12
LFRAME#/FWH4
470PF
C320
470PF
C317
0.1UF
C309
0.1UF
C321C348
0.1UF
C313
0.1UF 0.1UF
C323
2.2UF
C349
2
1
26 VCC5_KBMS_J
4.7K
R315
RP5 4.7K
1234
5678
CPU_TACH1
PCD PLATFORM DESIGN
REV:
DRAWN BY:
LAST REVISED:
PROJECT:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87654321
A
B
C
D
12345678
D
C
B
A
1.01
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
OF 36
R
VCC3_3
SIO
LPC47B27X
A20GATE
ACK#
ALF#
AVSS
BUSY
CLKI32
CLOCKI
CTS1#
CTS2#
DCD1#
DCD2#
DIR#
DRVDEN0
DRVDEN1
DS0#
DSKCHG#
DSR1#
DSR2#
DTR1#
DTR2#
ERROR#
FAN1/GP33
FAN2/GP32
FDC_PP/DDRC/GP43
GND1 GND2 GND3 GND4
GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
GP15/J1Y
GP16/J2X
GP17/J2Y
GP20/P17
GP21/P16
GP22/P12
GP25/MIDI_IN
GP26/MIDI_OUT
GP27/IO_SMI#
GP30/FAN_TACH2
GP31/FAN_TACH1
GP60/LED1
GP61/LED2
HDSEL#
INDEX#
INIT#
IRRX2/GP34
IRTX2/GP35
KBDRST
KCLK
KDAT
LAD0
LAD1
LAD2
LAD3
LDRQ#
LFRAME#
LRESET#
MCLK
MDAT
MTR0#
PCI_CLK PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
PME#
RDATA#
RI1#
RI2#
RTS1#
RTS2#
RXD1
RXD2_IRRX
SERIRQ
SLCT#
SLCTIN#
STEP#
STROBE#
TRK0#
TXD1
TXD2_IRTX
VCC1 VCC2 VCC3
WDATA#
WGATE#
WRTPRT#
VREF
GP24/SYSOPT
VTR
LPCPD#
SERIAL PORT 1
SERIAL PORT 2
FDC I/F
LPC I/F
INFRARED I/F
CLOCKS
KYBD/MSE I/F
PARALLEL PORT I/F
VCC3_3
VCC5
VCC5 VCC3_3
VCC3_3
+
Pulldown on SYSOPT for IO address of 0x02E
LPC header. For debug only.
Super I/O
Place decoupling caps near each power pin.Place next to VREF.