User's Manual

Introduction
1-4 Intel
®
820 Chipset Design Guide
I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system.
Additionally, it integrates many I/O functions. The ICH integrates the following functions:
•
Upstream hub interface for access to the MCH
•
2 channel Ultra ATA/66 Bus Master IDE controller
•
USB controller
•
I/O APIC
•
SMBus controller
•
FWH interface (FWH Flash BIOS)
•
LPC interface
•
AC’97 2.1 interface
•
PCI 2.2 interface
•
Integrated System Management Controller
•
Alert on LAN*
The ICH also contains the arbitration and buffering necessary to ensure efficient utilization of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information on these
interfaces.
ISA Bridge (82380AB)
For legacy needs, ISA support is an optional feature of the Intel
®
820 chipset. Implementations that
require ISA support can benefit from the enhancements of the Intel
®
820 chipset while “ISA-less”
designs are not burdened with the complexity and cost of the ISA subsystem.
The Intel
®
820 chipset platform with optional ISA support takes advantage of the 82380AB ISA
bridge. The bridge is a PCI to ISA bridge and resides on the PCI bus of the ICH.
1.3.2 Bandwidth Summary
Table 1-1 provides a summary of the bandwidth requirements for the Intel
®
820 chipset.
Table 1-1. Intel
®
820 Chipset Platform Bandwidth Summary
Interface
Clock Speed
(MHz)
Samples
Per Clock
Data Rate
(Mega-samples/s)
Data Width
(Bytes)
Bandwidth
(MB/s)
Processor Bus 133 1 133 8 1066
RDRAM 266/300/356/400 2 533/600/711/800 2 1066/1200/1422/1600
AGP 2.0 66 4 266 4 1066
Hub Interface 66 4 266 1 266
PCI 2.2 33 1 33 4 133