User's Manual

System Design Considerations

6-6 Intel

820 Chipset Design Guide

6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization

Tie a single core well GPO with a default high state to both the S0 and S1 pins of the DRCG

(i.e., tie S0 and S1 together and then connect to a GPO as shown in Figure 6-3). When the core

power supply to the system is turned on, the DRCG enters a test mode and the output frequency

will match the input REFCLK frequency. For details on this DRCG mode, refer to the latest DRCG

specification. By slowing down the DRCG output clock, the power consumption from the 2.5V

power supply is reduced. After the SetR/ClrR commands have been issued, the BIOS drives the

GPO low to bring the DRCG back to normal operation.

Note: If a default low GPO is used, on power up, all the devices may come up in the standby state at full

speed; thus, requiring more power.

6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage

Regulator

The second implementation option requires that the 2.5V power supply be modified to maintain the

maximum amount of current required by a fully populated RDRAM channel (~7.5A).

Figure 6-3. Use a GPO to Reduce DRCG Frequency

DRCG

GPO