User's Manual

Intel
®
820 Chipset Design Guide 6-3
System Design Considerations
In addition to the power planes provided by the ATX power supply, an instantly available Intel
®
820 chipset based system (using Suspend-to-RAM) requires 7 power planes to be generated on the
board. The requirements for each power plane are documented in this section. In addition to on-
board voltage regulators, the Intel
®
820 Chipset Reference Board will have a 5V Dual Switch.
5V Dual Switch
This switch powers the 5V Dual plane from the 5V core ATX supply during full-power operation.
During Suspend-to-RAM, the 5V Dual plane is powered from the 5V Standby power supply.
Note: The voltage on the 5V Dual plane is not 5V! There is a resistive drop through the 5V Dual Switch
that must be considered. Therefore, NO COMPONENTS should be connected directly to the 5V
Dual plane. On the Intel
®
820 chipset Reference Board, the only devices connected to the 5V Dual
plane are voltage regulators (to regulate to lower voltages).
Note: This switch is not required in a Intel
®
820 chipset based system that does not support Suspend-to-
RAM (STR).
VCC
VID
This power plane is used to power the SC242 processor. Refer to the latest revisions of:
•
VRM 8.4 DC-DC Converter Design Guidelines
•
Slot 1 Power Delivery Guidelines
Note: This regulator is required in ALL designs.
V
TT
This power plane is used to power the AGTL+ termination resistors. Refer to the latest revisions of:
•
Intel
®
Pentium
®
III Processor Datasheet
Note: This regulator is required in ALL designs.
2.5VSBY
The 2.5VSBY power plane is used to power the RDRAM core and the VCMOS rail on the
RDRAMs. The RDRAM core requires approximately 4.5A maximum average DC current at 2.5V
(refer to Section 6.1.3, “64/72Mbit RDRAM Excessive Power Consumption” on page 6-5). In the
Intel
®
820 Chipset Reference Board, the 2.5VSBY plane is derived from the 5V Dual power plane
using a switching regulator. It is important, that during the maximum load-step of 2A, the
maximum voltage fluctuation is less than 50 mV. The maximum 2.5V tolerance is 125 mV,
however during any 10 uS period, the voltage can not fluctuate more than 50 mV. The high-
frequency bypassing requirements are met using capacitors on the RIMM itself. Low frequency
bypass requirements vary depending on the voltage regulator used. Using a switching regulator,
with a relatively slow response time, the low frequency bypass recommendation is: 8 100 uF bulk
capacitors (0.1Ω ESR) near the RIMM connectors. These capacitors must be placed near the
RIMM connector. Preferably spread the capacitors around where 2.5V connects to the RIMMs.
The VCMOS rail requires a maximum of 3ma at 1.8V. This rail MUST be powered during
Suspend-to-RAM and therefore, the VCMOS rail can not be connected to the MCH core power.
Because the current requirements of VCMOS are so low, a resistor divider can be used to generate
VCMOS from 2.5VSBY. The resistor divider should be 36 Ω (top) / 100 Ω (bottom). Additionally,
it should be bypassed with a 0.1 µF chip capacitor.