User's Manual

Intel
®
820 Chipset Design Guide 1-3
Introduction
configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA
devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA
bridge.
The Intel
®
820 chipset contains two core components: the Memory Controller Hub (MCH) and the
I/O Controller Hub (ICH). The MCH integrates the 133 MHz processor system bus controller,
AGP 2.0 controller, 400 MHz Direct RDRAM controller and a high-speed hub interface for
communication with the ICH. The ICH integrates an UltraATA/66 controller, USB host controller,
LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller, AC’97
digital controller and a hub interface for communication with the MCH. The Intel
®
820 chipset
provides the data buffering and interface arbitration required to ensure that system interfaces
operate efficiently and provide the system bandwidth necessary to obtain peak performance with
the Pentium III processor.
1.3.1 Chipset Components
This section provides an overview of the 82820 Memory Controller Hub (MCH) and the 82801AA
I/O Controller Hub (ICH). Additional functionality can be provided using the 82380AB PCI-ISA
bridge.
Memory Controller Hub (MCH)
The MCH provides the interconnect between the Direct RDRAM and the system logic. It integrates
the following functions:
•
Support for single or dual SC242 processors with 100 MHz or 133 MHz System Bus
•
256 MHz, 300 MHz, 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB of
Direct RDRAM
•
4X, 1.5V AGP interface (3.3V 1X, 2X and 1.5V 1X, 2X devices also supported)
•
Downstream hub interface for access to the ICH
In addition, the MCH provides arbitration, buffering and coherency management for each of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information regarding these
interfaces.