User's Manual

Intel
®
820 Chipset Design Guide 5-3
System Manufacturing
5.3.4 Test Coupon Design Guidelines
Characterization and understanding of the trace impedance is critical for delivering reliable
systems at the increased bus frequencies. Incorporating a test coupon design into the motherboard
makes testing simpler and more accurate. The test coupon pattern must match the probe type being
used.
The location of the test coupon is listed in order of preference below:
•
1
st
Choice (Ideal Location) = Memory section of the motherboard
•
2
nd
Choice = Any section of the motherboard
•
3
rd
Choice = Separate location in the panel
The Intel Impedance Test Methodology Document should be used to ensure boards are within the
28Ω ±10% requirement. The Intel Controlled Impedance Design and Test Document should be
used for the test coupon design and implementation. These documents can be found at:
http://developer.intel.com/design/chipsets/memory/rdram.htm
— Select “Application Notes”
5.3.5 Recommended Stackup
Though numerous variations of stackup are possible, it is recommended that the following should
be used as a starting point:
W=18 mil, H=4.5 mil, T=2.0, 1 ply 2116 pre-preg
For other possibilities see Table 5-1 and following figures:
5.3.6 Inner Layer Routing
Inner Layer Routing also has many possible stackups. For Inner Layer Routing, it is recommended
to use the following as a starting point:
W=13.5 mil, H1=7 mil, H2=5, T=1.2
With these parameters, initial TDR should fall within acceptable limits - 28 Ω ±10%
Figure 5-2 shows examples of both Stripline and Microstrip cross sections.
Table 5-1. 28Ω Stackup Examples
Sample Zo H W T SM(max) Resin %
1 27.1 4.3 18.0 2.1 0.6 53.0
2 28.1 3.8 18.5 1.6 1.2 72.0
3 28.6 4.8 19.0 2.5 0.7 61.0