User's Manual
Intel
®
820 Chipset Design Guide 4-13
Clocking
2. The Intel
®
820 chipset supports the following ratios and can be supported by the DRCG and
DRCG+ or derivative devices. Contact your DRCG vendor for information on DRCG,
DRCG+, and derivative products.
3. The jitter timing specifications are expanded to encompass both the component specification
(for DRCG or derivative products) and the channel specification. Follow the component
specification when measuring jitter at the DRCG output resistor. Follow the channel jitter
guidelines when measuring jitter at the MCH or at the termination for CFM/CFM# on the
RDRAM interface.
4.8.2 DRCG+ Frequency Selection Schematic
DRCG+ frequency selection can be accomplished using two GPIOs connected to the MULT[0:1]
pins as shown in Figure 4-11. This allows selection of all frequencies supported by the Intel
®
820
chipset.
100 MHz Host Bus 133 MHz Host Bus
Frequency Multiplier Frequency Multiplier
100 / 300 6:1 133 / 266 4:1
100 / 400 8:1 133 / 356 16:3
133 / 400 6:1
Output Frequency
(MHz)
Component Jitter
Specification
Channel Jitter
Guidelines
400 50 ps 100 ps
356 60 ps 110 ps
300 70 ps 120 ps
266 80 ps 130 ps
Figure 4-11. DRCG+ Frequency Selection
REFCLK
PWRD#
STOPB#
MULTO
MULT1
S0
S1
GND
PCLKM
SYNCLKN
NC
2
12
11
15
14
24
23
13
6
7
19
GPO1
GPO2
17
21
4
8
5
GNDO1
GNDO2
GNDP
GNDC
GNDI
CLK
CLKB#
20
18
1
10
16
22
3
9
VDDIR
VDDIPD
VDDO1
VDDO2
VDDP
VDDC
U?
DRCG