User's Manual

Clocking
4-10 Intel
®
820 Chipset Design Guide
4.3 DRCG Impedance Matching Circuit
The external DRCG impedance matching circuit is shown in Figure 4-9. The values for the
elements are listed in Table 4-5.
NOTES:
1. The ferrite bead and 10 uF bulk cap combination improves jitter and helps to keep the clock noise away from
the rest of the system.
2. 0.1 uF capacitors are better than 0.01 uF or 0.001 uF caps for DRCG decoupling.
The circuit shown in Figure 4-9 is required to match the impedance of the DRCG to the 28 Ω
channel impedance. More detailed information can be found in the Direct Rambus Clock Generator
Specification.
Figure 4-9. DRCG Impedance Matching Network
DRCG
C
D
R
S
R
P
R
T
Z
CH
C
F
V
DD
V
DD
O
V
DD
O
C
D
R
S
C
MID
R
P
Z
CH
C
MID2
R
T
IR
V
DD
P
V
DD
V
DD
C
IPD
C
D
C
D
C
D
C
D
3.3v
FBead
CBulkCD2
CD2
To 3.3V DRCG
Supply Connection
Table 4-5. External DRCG Component Values
1,2
Component Nominal Value Notes
C
D
0.1 uF Decoupling caps to ground
R
S
39 Ohms Series termination resistor
R
P
51 Ohms Parallel termination resistor
C
MID
, C
MID2
0.1 uF Virtual ground caps
R
T
27 Ohms End of channel termination
C
F
4 pF Do not stuff
FBead 50 Ohms at 100 MHz Ferrite bead
CD2 0.1 uF Additional 3.3V decoupling caps
CBulk 10 uF Bulk cap on device side of ferrite bead