User's Manual

Clocking
4-8 Intel
®
820 Chipset Design Guide
4.2.4 DRCG to RDRAM Channel
The Direct Rambus* clock signals (CTM/CTM# and CFM/CFM#) are high-speed, impedance
matched transmission lines. The Direct Rambus* clocks begin at the end of the Direct Rambus*
channel and propagate to the controller as CTM/CTM# (see Figure 4-5), where it loops back as
CFM/CFM#. Table 4-4 lists the placement guidelines.
NOTE: * Refer to Figure 4-5
Trace Geometry
In Sections labeled ‘A’ and ‘D’ (Figure 4-5) the clock signals (CTM/CTM# and CFM/CFM#) must
be 14 mils wide and routed as shown in Figure 4-6. For all other sections (‘B’ and ‘C’) the clock
signals must be routed with 18 mil wide traces. There must be a 22 mil ground isolation trace
routed around the clock differential pair signals. The 22 mil ground isolation traces must be
connected to ground with a via every 1”. A 6 mil gap is required between the clock signals and the
ground isolation traces. For the section labeled “A” in Figure 4-5, 0.021 inches of CLK per 1 inch
of RSL trace length must be added to compensate for the clocks faster trace velocity as described in
Section 2.6.2.1, “RSL Routing” on page 2-8. The CTM/CTM# and the CFM/CFM# differential
signal pairs must be length matched to ±2 mils in line section labeled ‘A’ and for the line sections
labeled ‘B’ using the trace length methods in Section 2.6.2.1, “RSL Routing” on page 2-8. For the
section labeled ‘D’ the trace length matching for CTM/CTM# is ±2 mils, and for the section
labeled ‘C’, ±2 mil trace length matching is required for the CFM/CFM# signals.
The CTM/CTM# signals must be ground referenced (with a continuous ground island/plane) from
the DRCG to the Last RIMM.
4.2.5 Trace Length
For the section labeled “A” in Figure 4-5 (1
st
RIMM to MCH and MCH to 1
st
RIMM),
CTM/CTM# and CFM/CFM# must be length matched within ±2 mils (exact trace length matching
is recommended). Package trace compensation (as described in Section 2.6.2.1, “RSL Routing”
on page 2-8), via compensation, and RSL signal layer alternation must also be completed on
the clock signals. Additionally, 0.021 inches of CLK per 1 inch of RSL trace length must be added
to compensate for the clocks faster trace velocity as described in Section 2.6.2.1.
For the line sections labeled ‘B’ (Figure 4-5) (RIMM to RIMM) the clock signals must be matched
within ±2 mils to the trace length of every RSL signal. Exact length matching is preferred.
Table 4-4. Placement Guidelines for Motherboard Routing Lengths
Direct Rambus* Clock Routing Length Guidelines
Clock From To Length (inches) Section*
CTM/CTM# DRCG Last RIMM Connector 0.000 – 6.000 D
RIMM RIMM 0.400 – 0.450 B
1
st
RIMM Connector Chipset 0.000 – 3.500 A
CFM/CFM# Chipset 1
st
RIMM Connector 0.000 – 3.500 A
RIMM RIMM 0.400 – 0.450 B
Last RIMM Connector Termination 0.000 – 3.000 C