User's Manual

Intel
®
820 Chipset Design Guide 4-7
Clocking
4.2.3 MCH to DRCG
•
PclkM
•
PclkN
•
VddIPD
The Hclkout, Rclkout and VddiPD should be routed as shown in Figure 4-4. Note that the VddiPD
pin can be connected directly to 1.8V near the DRCG if the 1.8V plane extends near the DRCG.
However, if a 1.8V trace must be run, it should originate at the MCH and be routed as shown.
The maximum length for Hclkout and Rclkout is 6”. Additionally, Hclkout and Rclkout must be
length matched (to each other) within 50 mils. These signals should be routed on the same layer. If
the signals must switch layers, then BOTH signals should change layers together.
If VddiPD is connected to the 1.8V plane using a via (e.g., a trace is not run from the MCH),
Hclkout and Rclkout must still be routed differentially and ground isolated.
Figure 4-4. MCH to DRCG Routing Diagram
Ground
Ground/Power Plane
6 mils
4.5 mils
1.4 mils
1.4 mils
6 mils
VddiPD
6 mils
6 mils
Ground
6 mils
6 mils
Hclkout
6 mils
6 mils
Rclkout
6 mils
6 mils
Ground
6 mils
Figure 4-5. Direct Rambus* Clock Routing Dimensions
blkt
MCH
RIMM_0 RIMM_1
A B C
0"-3.50"
0.4"-0.45"
0"-3"
DRCG
D
(A) = CTM/CTM# RIMM to MCH
(A) = CFM/CFM# MCH to RIMM
(B) = RIMM to RIMM for Clocks
(C) = RIMM to Termination
(D) = DRCG to RIMM
CFM/CFM#
CTM/CTM#
0"-6"
Term